Chaitanya Goteti

Software Engineer

Hyderabad, Telangana, India9 yrs 10 mos experience
Highly Stable

Key Highlights

  • 7+ years of experience in IP and SoC verification.
  • Expertise in UVM based verification and architecting testbenches.
  • Mentored students on advanced verification methodologies.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in UVM and SoC technologies.

Contact

Skills

Core Skills

UvmSoc

Other Skills

Memory BIST verificationSoC Power management verificationPythonVLSISystemVerilogShell ScriptingFPGAProgrammingVery-Large-Scale Integration (VLSI)Application-Specific Integrated Circuits (ASIC)SemiconductorsUnixCperlVerilog

About

7+ years of experience in IP and SoC verification * 4 years of experience in ARM CPU verification * Expertise in UVM based verification. Experience in architecting UVM testbench from scratch * Worked on SoC power management verification for AMD which involves verfying the power/reset states of core and other components of multiple SoCs * Mentored students on UVM and perl * Worked on Memory BIST verification

Experience

9 yrs 10 mos
Total Experience
2 yrs
Average Tenure
1 yr 10 mos
Current Experience

Amd

Member of Technical Staff

Jul 2024Present · 1 yr 10 mos · Hyderabad, Telangana, India · On-site

Arm

2 roles

Senior Verification Engineer

Promoted

Oct 2021Jun 2024 · 2 yrs 8 mos

Verification Engineer

Nov 2019Sep 2021 · 1 yr 10 mos

Soctronics

2 roles

Engineer 2

Apr 2019Oct 2019 · 6 mos

Engineer 1

Jan 2017Mar 2019 · 2 yrs 2 mos

  • Currently working on SoC Power management verification which involves verifying different core and system power states, clocks and resets
  • Previously worked on Memory BIST verification where I had the responsibility of creating tests, sequences and testbench components like drivers, scoreboard, monitors etc. We developed the complete verification environment from scratch using UVM. Also we used vManager to collect coverage
UVMMemory BIST verificationSoC Power management verificationSoC

Vedaiit

Trainee in logic design

Jul 2016Dec 2016 · 5 mos · Hyderabad Area, India

  • This training helped me learn Verilog, System verilog, perl, tcl, C, C++ and made me industry ready

Tata consultancy services

Assistant systems engineer-Trainee

Jan 2014Jun 2014 · 5 mos · Greater Bengaluru Area

  • Front end support

Education

ABV-Indian Institute of Information Technology and Management

Master of Technology (M.Tech.) — VLSI

Jan 2014Jan 2016

ANIL NEERUKONDA INSTITUTE OF TECHNOLOGY AND SCIENCES

Bachelor of Engineering (BE) — Electronics and Communications Engineering

Jan 2009Jan 2013

Aditya Junior College

10+2

Jan 2007Jan 2009

Sri Vasista School

High school — Mathematics

Jan 1995Jan 2007

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