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Chandrani Pal

Director of Engineering

Bengaluru, Karnataka, India23 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 20+ years in semiconductor IP design leadership
  • Expert in building high-performing engineering teams
  • Proven track record in delivering optimized Hard IP products
Stackforce AI infers this person is a semiconductor industry leader with extensive experience in IP design and engineering management.

Contact

Skills

Core Skills

Ip DesignTeam LeadershipProject ManagementPhysical DesignTeam ManagementDesign AutomationMethodology DevelopmentFlow DevelopmentMethodology Implementation

Other Skills

TimingLogic SynthesisAPR of logic blocksIP backend sign offSoCStatic Timing AnalysisEDALogic DesignSignal IntegrityAnalogIntelSemiconductorsASIC

About

Engineering leader with 20+ years of rich & insightful experience in Industry leading High Speed Hard IP designs, powering semiconductor products across Client, Server, AI, Networking, Communications market segments. Excellence in building results-driven, high performing IP design organizations, and ensuring scalable, high quality & robust technologies/methodologies to meet business objectives. Ability to build and guide engineering teams comprising of diverse and geographically distributed resources. Excellence in setting up best practices and overseeing adoption & acceptance of the same for larger organizational goals. Consistent track record of delivering differentiated Hard IP Products and Systems on cutting edge process technology nodes. Currently leading 150+ members Intel Hard IP Development group in Bangalore, responsible for delivering Best-in-class Power/Performance/Area optimized Hard IPs, powering Intel Products. Competencies: Strategic Planning, Multi-site Project management, Outsourced Project Management, Risk Management, Budget Management, People Development, Cross-functional Collaboration, Quality Assurance, Influencing EDA Vendors for best-in-class tools/methodologies in Semiconductor Industry

Experience

23 yrs 3 mos
Total Experience
7 yrs 9 mos
Average Tenure
17 yrs 3 mos
Current Experience

Intel technology india pvt ltd

5 roles

Senior Director, Hard IP Development

Promoted

Jan 2025Present · 1 yr 3 mos

  • Senior Director, Hard IP Development, Central Engineering Group, Intel
TimingLogic SynthesisAPR of logic blocksIP backend sign offSoCStatic Timing Analysis+9

Director of Engineering

Promoted

Jan 2019Jan 2024 · 5 yrs

  • Hard IP Development group in Bangalore, responsible for delivering Best-in-class Power/Performance/Area optimized Hard IPs, powering Intel Products.
TimingLogic SynthesisAPR of logic blocksIP backend sign offSoCStatic Timing Analysis+9

Design Manager

Promoted

Jan 2010Jan 2018 · 8 yrs · Bangalore

  • Working on High speed serial IOs, managing backend physical design and custom layout teams. Responsible for physical design and sign off for logic design blocks, analog CKT building blocks custom layout sign off and overall IP family integration/ backend sign off which includes timing, reliability verification, layout verification and low power sign off.
TimingLogic SynthesisAPR of logic blocksIP backend sign offSoCStatic Timing Analysis+9

Engineering Manager - Design Automation

Promoted

Jan 2006Jan 2009 · 3 yrs

  • Responsible for leading and managing Design Automation team in Bangalore that is responsible for developing synthesis, place & route and timing, noise, reliability analysis, low power design methodologies for Intel and external foundry processes.
TimingLogic SynthesisAPR of logic blocksIP backend sign offSoCStatic Timing Analysis+9

Senior Member Technical Staff

Jan 2001Jan 2005 · 4 yrs

  • Technical lead for developing flows and methdologies in the areas of crosstalk noise, delay, STA, crosstalk optimization using P&R tools for Intel DSM processes. Capabilities delivered are deployed across several SOC projects at Intel.
TimingLogic SynthesisAPR of logic blocksIP backend sign offSoCStatic Timing Analysis+9

Texas instruments india

CAD Engineer

Jan 1998Jan 2000 · 2 yrs

Education

Manipal Academy of Higher Education

MS — VLSI-CAD

Jan 2004Jan 2006

IIEST, Shibpur

Bachelor of Engineering (B.E.) — Computer Science and Technology

Jan 1994Jan 1998

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