Manish Kumar

Software Engineer

Noida, Uttar Pradesh, India9 yrs 5 mos experience

Highly Stable

Key Highlights

Expert in VLSI design with a focus on advanced nodes.
Led development of 5nm processors for automotive applications.
Proficient in physical synthesis and static timing analysis.

Stackforce AI infers this person is a VLSI design expert in the automotive industry.

Contact

Skills

Core Skills

Physical DesignStaNetworking

Other Skills

Physical SynthesisLow-power DesignDesign constraints developmentTiming ClosureConstraint developmentNetworking ConceptsSecurity TechnologyJavaCMatlabMicrosoft ExcelMicrosoft WordMicrosoft OfficeMicrosoft PowerPointPython

About

Staff Engineer | Qualcomm B.Tech in ECE from NIT Patna with expertise in VLSI design. Skilled in physical synthesis, constraints development, signoff STA (block and top level), and timing/functional ECOs. Experienced with Synopsys tools, Unix Shell, and TCL scripting. Worked on 5 nm ADAS processors for automotive applications. Currently working on 2 nm technology.

Experience

9 yrs 5 mos

Total Experience

3 yrs

Average Tenure

2 mos

Current Experience

Qualcomm

Staff Engineer

Mar 2026 – Present · 2 mos · Noida, Uttar Pradesh, India · On-site

Physical SynthesisLow-power DesignDesign constraints developmentSTATiming ClosurePhysical Design

Stmicroelectronics

Staff Engineer

Aug 2019 – Feb 2026 · 6 yrs 6 mos · Noida Area, India · On-site

Staff Engineer | STMicroelectronics
Experienced in leading advanced node physical design efforts, currently working on 5nm ADAS 4 & 5 processor development for branded automotive platforms. Skilled in block-level physical synthesis, constraint development, and static timing analysis (STA). Proficient in IO timing analysis and cross-block timing ECOs at the full-chip level. Hands-on expertise in implementing functional ECOs, clock ECOs, and setup/hold timing fixes to meet aggressive PPA and tape-out goals. Proven ability to drive complex design cycles under strict automotive-grade standards.

STAPhysical SynthesisPhysical Design

Wipro limited

Project Engineer

Oct 2017 – Jul 2019 · 1 yr 9 mos · Hyderabad Area, India

Worked in Wipro (PES-VLSI), handling Intel Projects, rdt flow, low power design, 14nm technology node. Well versed with block level Physical Synthesis, Floorplan, Place & Route, STA and Physical Verification, IO timing analysis and fixes between multiple blocks from full chip level. Hand on experience in functional ECO implementation, clock ECOs, Setup & Hold fixes.

Physical Design

Hewlett packard enterprise

Trainee

Jun 2016 – Jul 2016 · 1 mo · Patna Area, India

Trained in Networking Concepts with security.
Major Project -
“Corporate network with advance routing, switching and security” designed on Networking Concepts with Security Technology during HPE Summer Training Programme.
 Basic Configuration: Consist of 12 Routers, 11 Switches, 2 Multi-Layer Switches, 2 Servers, 1 DNS, 29 PCs,
 Routing Protocol: EIGRP
 Layer-Switches: Used as VTP Servers
 Security: VLAN for Switches, Static NAT, Dynamic NAT, PAT
 Server: Used with fake IP.

Indian oil corporation limited

Intern

May 2016 – Jul 2016 · 2 mos · IOCL PATNA TERMINAL

Trained on Industry Automation System. Worked on various projects with under IOCL and L&T Engineers on setting up Automated Position Sensors on the Mechanical Loading Arms, fixing batch controllers, feeding NVRAM memory with required parameter in batch controller's CPU card, fixed signal interruption problems in communication between batch controller and LRCS server.

Ishan international public school

Headboy

Apr 2011 – Mar 2012 · 11 mos · Kankarbagh, Patna, Bihar

I had been the Headboy of my school in 12th std. Got selected after three consecutive rounds of selection including Nomination, Critical thinking Test by giving on spot topic to speak in front of whole school and Personal Interview.