V

Vinay Bollu

Director of Engineering

Bengaluru, Karnataka, India20 yrs 6 mos experience
Highly Stable

Key Highlights

  • Experienced in Physical Design Engineering at Intel.
  • Expertise in Low-power Design and Physical Verification.
  • Strong background in ASIC implementation methodologies.
Stackforce AI infers this person is a Physical Design Engineering expert in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Physical DesignImplementation MethodologyLow-power Design

Other Skills

Application-Specific Integrated Circuits (ASIC)Place & RouteIC CompilerClock Tree SynthesisTiming ClosurePower AnalysisPhysical VerificationFloorplanningBumpCMOSDRCLVS

Experience

20 yrs 6 mos
Total Experience
12 yrs 2 mos
Average Tenure
8 yrs 4 mos
Current Experience

Intel corporation

2 roles

Physical Design Engineering Manager

Promoted

May 2024 – Present · 1 yr 11 mos

Implementation MethodologyApplication-Specific Integrated Circuits (ASIC)Place & RouteIC CompilerClock Tree SynthesisTiming Closure+9

Physical Design Engineer

Dec 2017 – May 2024 · 6 yrs 5 mos

Low-power DesignPhysical Verification

Cypress semiconductor

Sr Staff Elect Design Engr

Oct 2005 – Dec 2017 · 12 yrs 2 mos · Bengaluru Area, India

Low-power DesignPhysical Verification

Education

M S RAMAIH SCHOOL OF ADV STUDIES

MS — VLSI

NTTF Electronics Training Center

Diploma — Electronics

Jan 2001 – Jan 2004

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