Jai S.

Software Engineer

Noida, Uttar Pradesh, India5 yrs 3 mos experience

Most Likely To Switch

Key Highlights

Experienced in DFT and SoC design.
Strong background in verification methodologies.
Gold medalist in BTech, showcasing academic excellence.

Stackforce AI infers this person is a skilled engineer in the semiconductor and EDA industry.

Contact

Skills

Core Skills

DftVerilog

Other Skills

TessentSystemVerilogQuestaSimSpyglassAutomatic Test Pattern Generation (ATPG)MatlabWindowsLinuxCentOSCDigital Image ProcessingUniversal Verification Methodology (UVM)Digital Signal ProcessingViTestkompress

Experience

5 yrs 3 mos

Total Experience

1 yr 9 mos

Average Tenure

2 yrs 7 mos

Current Experience

Synopsys inc

2 roles

Staff Engineer

Feb 2024 – Present · 2 yrs 3 mos

Solution engineer Sr 1

Oct 2023 – Feb 2024 · 4 mos

Intel corporation

SoC Design Engineer

Jul 2022 – Oct 2023 · 1 yr 3 mos · Bengaluru, Karnataka, India

TessentDFT

Siemens eda (siemens digital industries software)

2 roles

Sr. Corporate Application Engineer

Promoted

May 2022 – Jul 2022 · 2 mos

Corporate Application Engineer

Dec 2020 – May 2022 · 1 yr 5 mos

CAE - DFT

Mentor graphics

2 roles

DFT intern

Mar 2020 – Dec 2020 · 9 mos · Bengaluru, Karnataka

HEP SV trainee

May 2019 – Jul 2019 · 2 mos · Noida Area, India

HEP is a training program by mentor graphics . In this training verilog / system verilog are taught with projects such as verification of LC3 microprocessor using Questasim