Prathamesh Chodankar — Software Engineer
Myself Prathamesh Chodankar, I have M.Tech Degree in VLSI Design from Vellore Institute of Technology(VIT) Vellore, Tamil Nadu, India and currently I am working in CPUSS RTL Design team at Intel, India with experience of ~8 years. In my total experience in Qualcomm & Intel, I have worked in both ARM & Intel Architectures to deliver high quality CPUSS RTL to SOC. over the time I have gained experience in IP/SubSystem integration and also IP development. I have micro-architected so far 3 ARM based CPUSS in Intel and they have been successfully verified. In Intel, as part of leading the CPUSS design team, I was managing 3 team members as well. thus I have gained management experience as well. Recently, I am leading the CCF(converged Coherent Fabric) IP development effort with 5 other colleagues for Intel's latest Server chip. . Technical Skills : 1) EDA TOOLS :Synopsys Spyglass, Cadence Jaspergold , Cadence DMV, Cadence NCLaunch, Cadence Virtuoso Spectre Circuit Simulator, RTL Compiler, SoC Encounter, Virtuoso Schematic Editor, Cadence Virtuoso Analog Design Environment. 2) HARDWARE DESCRIPTION LANGUAGE: Verilog HDL. 3) SCRIPTING LANGUAGE: Perl. 4) SOFTWARE LANGUAGES: C, C++, MATLAB. 5) DESIGN TOOLS : ModelSim 6.6d 6) FPGA SYNTHESIS TOOLS : Xilinx ISE, ALTERA-Quartus II 7) FPGA HARDWARE IMPLEMENTATION: Altera Cyclone II Design Kit. 8) DEVICE MODELLING AND SIMULATION : Silvaco TCAD Areas of Interest : 1) RTL Design 2) Automation using Perl Programming 3) Verification and Testing using Verilog HDL. 4) Static timing Analysis 5) Physical Design.
Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in RTL and SoC development.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 10 mos
Skills
- Low-power Design
- System On A Chip (soc)
Career Highlights
- 8 years of experience in VLSI Design.
- Led CPUSS design team at Intel.
- Expertise in ARM and Intel architectures.
Work Experience
Qualcomm
Staff Engineer (3 yrs 1 mo)
Intel Corporation
Sr. SOC Design Engineer (2 yrs 11 mos)
SOC Design Engineer (2 yrs)
Qualcomm
Senior Engineer (4 mos)
Engineer (1 yr 5 mos)
Cadence Design Systems
Design Engineer (1 yr 1 mo)
Education
Master of Technology (MTech) at Vellore Institute of Technology
Bachelor of Engineering (B.E.) at University of Mumbai