Prathamesh Chodankar

Software Engineer

Bengaluru, Karnataka, India10 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 8 years of experience in VLSI Design.
  • Led CPUSS design team at Intel.
  • Expertise in ARM and Intel architectures.
Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in RTL and SoC development.

Contact

Skills

Core Skills

Low-power DesignSystem On A Chip (soc)

Other Skills

CDCRTL DevelopmentRTL CodingVerilogCC++Cadence SpectreCadence VirtuosoCadence Virtuoso Layout EditorCadence nclaunchCadence rtl compilerAltera QuartusModelSimVLSIXilinx

About

Myself Prathamesh Chodankar, I have M.Tech Degree in VLSI Design from Vellore Institute of Technology(VIT) Vellore, Tamil Nadu, India and currently I am working in CPUSS RTL Design team at Intel, India with experience of ~8 years. In my total experience in Qualcomm & Intel, I have worked in both ARM & Intel Architectures to deliver high quality CPUSS RTL to SOC. over the time I have gained experience in IP/SubSystem integration and also IP development. I have micro-architected so far 3 ARM based CPUSS in Intel and they have been successfully verified. In Intel, as part of leading the CPUSS design team, I was managing 3 team members as well. thus I have gained management experience as well. Recently, I am leading the CCF(converged Coherent Fabric) IP development effort with 5 other colleagues for Intel's latest Server chip. . Technical Skills : 1) EDA TOOLS :Synopsys Spyglass, Cadence Jaspergold , Cadence DMV, Cadence NCLaunch, Cadence Virtuoso Spectre Circuit Simulator, RTL Compiler, SoC Encounter, Virtuoso Schematic Editor, Cadence Virtuoso Analog Design Environment. 2) HARDWARE DESCRIPTION LANGUAGE: Verilog HDL. 3) SCRIPTING LANGUAGE: Perl. 4) SOFTWARE LANGUAGES: C, C++, MATLAB. 5) DESIGN TOOLS : ModelSim 6.6d 6) FPGA SYNTHESIS TOOLS : Xilinx ISE, ALTERA-Quartus II 7) FPGA HARDWARE IMPLEMENTATION: Altera Cyclone II Design Kit. 8) DEVICE MODELLING AND SIMULATION : Silvaco TCAD Areas of Interest : 1) RTL Design 2) Automation using Perl Programming 3) Verification and Testing using Verilog HDL. 4) Static timing Analysis 5) Physical Design.

Experience

10 yrs 10 mos
Total Experience
2 yrs 8 mos
Average Tenure
3 yrs 1 mo
Current Experience

Qualcomm

Staff Engineer

Mar 2023Present · 3 yrs 1 mo · Bengaluru, Karnataka, India · Hybrid

  • Next generation Nuvia/Arm core cpuss.
CDCLow-power Design

Intel corporation

2 roles

Sr. SOC Design Engineer

Promoted

Apr 2020Mar 2023 · 2 yrs 11 mos

  • Leading CPU subsystem design on both Arm & Intel Architecture.
System on a Chip (SoC)RTL Development

SOC Design Engineer

Apr 2018Apr 2020 · 2 yrs

Qualcomm

2 roles

Senior Engineer

Promoted

Dec 2017Apr 2018 · 4 mos

Engineer

Jul 2016Dec 2017 · 1 yr 5 mos

Cadence design systems

Design Engineer

Jun 2015Jul 2016 · 1 yr 1 mo · Bengaluru Area, India

Education

Vellore Institute of Technology

Master of Technology (MTech) — VLSI Design

Jan 2013Jan 2015

University of Mumbai

Bachelor of Engineering (B.E.)

Jan 2008Jan 2012

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