Jan 2023 – Present · 3 yrs 4 mos

Jan 2017 – Apr 2023 · 6 yrs 3 mos

• Highlights:
• Responsible for leading a team to verify the ASIC design, architecture and micro-architecture using advanced verification methodologies.
• Architect efficient algorithms in C++ for models that would provide static as well dynamic stimulus for design under test.
• Analyze C++ code to identify and improve performance and at the same time identify coverage holes in the design.
• Responsible for keeping the quality of the code owned by my team to be of the highest standards
• Finalize and understand the design and implementation, define the verification scope, test plan & milestones, delegate and coordinate tasks within the whole verification team.
• Develop verification infrastructure and verify the correctness of the design.
• Constantly working with architects, designers, pre- and post- silicon verification teams to accomplish the tasks.

Oct 2015 – Jan 2017 · 1 yr 3 mos

• Highlights/Gained experience in :
• Architect for various C++ based test bench environments for unit and system level verification
• Designing constraint random testbench & testcases.
• Functional coverage driven methodology
• Design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Improving/Enhancing the DV infrastructure that impacts a wider audience

Jan 2013 – Oct 2015 · 2 yrs 9 mos

• Highlights:
• Verified complex IP's
• Developed new automation flows to run regressions
• Driving verification for start to end for new features in the ASIC chip
• Implement efficient algorithms in C++ for models that would provide static as well dynamic stimulus for design under test.
• Gained extensive experience in C++ programming