Renjith Rajan — Software Engineer
• Experience in RTL design using Verilog for IP and SOC • Working Experience in IOT and VIDEO Codec projects • ASIC design Flow • Design Experience in Low power SOC’s • Chip level integration and connectivity • Spyglass Lint,CDC for full chip/IPs, report analysis and bug fixing • ECO and LEC runs • Experience in micro architecture, design and unit level testing of IP’s with AXI AMBA protocol • Working closely with DV, BE and DFT team, and updating RTL based on feedback • Responsible for delivering compiled and sanity clean database for DV and BE • Experience in UPF • Writing Post Silicon bringup tests . • Experience in writing Python, Perl and Tcl scripts • Experience in working with GIT
Stackforce AI infers this person is a skilled ASIC design engineer with expertise in RTL design and low power SOCs.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 8 mos
Skills
- Asic Design
- Rtl Design
Career Highlights
- Expert in RTL design and ASIC development.
- Proficient in low power SOC design and integration.
- Strong scripting skills in Python, Perl, and Tcl.
Work Experience
Infineon Technologies
ASIC Design Engineer (3 yrs 7 mos)
Wafer Space
RTL Design Engineer (4 yrs 1 mo)
Atria Logic Inc.
RTL Design Engineer (2 yrs 5 mos)
collage of engineering,kidangoor
MTech ,Wireless Technology (2 yrs)
Education
Bachelor's degree at Mahatma Gandhi University
BTech-Electronics and Communication at adi shankara institute of engineering and technology
