Shakti Dutta Pattnaik

Software Engineer

Bengaluru, Karnataka, India18 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in DFT and ATPG methodologies.
Proven track record in silicon failure analysis.
Strong background in scan insertion techniques.

Stackforce AI infers this person is a Semiconductor DFT Engineer with extensive experience in ATPG and scan insertion.

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Skills

Core Skills

DftAtpg

Other Skills

ASICAutomatic Test Pattern Generation (ATPG)BISTDFT CompilerDigital DesignFastscanModelSimNCSimScan InsertionSimulationsSoCStatic Timing AnalysisSystem on a Chip (SoC)TetramaxTiming

About

• ATPG – Creating test sets for Stuck-At, Transition fault models. Verification of generated test patterns and debugging simulation mismatches. • MBIST - Insertion, verification for different algorithms. • Coverage Improvement analysis. • Scan Insertion. • IDDQ constraints and sequence validation. • Testmode timing constraints. • Implementing ECOs. • Checking RTL in Spyglass in order to clean DFT related rules, particularly clock and reset. • Checking Formal Verification at different phases. • Analyzing Low Power issues (LS and Isolation rules). • Knowledge on BIST and standard BIST algorithms. • Knowledge on JTAG and Boundary Scan. • Silicon Failure Analysis. • Knowledge of ASIC design flow

Experience

18 yrs 8 mos

Total Experience

3 yrs 2 mos

Average Tenure

8 yrs 10 mos

Current Experience

Mediatek

DFT Engineer

Jul 2017 – Present · 8 yrs 10 mos · Bengaluru, Karnataka, India · On-site

VLSI

ASICATPGAutomatic Test Pattern Generation (ATPG)BISTDFTDFT Compiler+17

Qualcomm

Senior Engineer

Apr 2013 – Jul 2017 · 4 yrs 3 mos · Bengaluru, Karnataka, India

Scan Insertion for HMs and SoC.
ATPG for Stuck-at and TDF.
Coverage Improvement.
Formal Verification.
Cleaning DFT related rules in RTL using Spyglass.
Testmode timing constraints.
IDDQ constraints and sequence validation, analyzing higher current reading through emission.
Analysing low power issues.
Implementing ECOs.
Simulation debug.
Silicon failure Analysis.

Synapse design automation inc.

Sr. DFT Engineer

Jun 2011 – Mar 2013 · 1 yr 9 mos · Bangalore, India

Worked for STM. ATPG for Stuck-at and Bridging Fault Models. Pattern Simulation in NoTiming and Timing environments, Fault Grading, Silicon failure analysis.