V

Vijay C P

Software Engineer

Bengaluru, Karnataka, India11 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Physical Design and Static Timing Analysis.
  • Proficient in Innovus and Cadence tools.
  • Strong background in VLSI and ASIC design.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and VLSI.

Contact

Skills

Core Skills

Physical DesignStatic Timing AnalysisInnovusDigital Design

Other Skills

Leadership DevelopmenttempusTiming AnalysisVerilogRoutingP&RASICVLSICIntegrated Circuit DesignSoCLinuxSemiconductorsCadence innovusCadence tempus

About

Working in Marvell semiconductors (Client)

Experience

11 yrs 2 mos
Total Experience
1 yr 11 mos
Average Tenure
5 yrs 6 mos
Current Experience

Mediatek

2 roles

Senior Staff Engineer

Jun 2025Present · 10 mos · Bengaluru, Karnataka, India

Senior Physical Design Engineer

Nov 2020Present · 5 yrs 5 mos · Bengaluru, Karnataka, India

Physical DesignStatic Timing AnalysisInnovusLeadership Development

Spicaworks

Senior Physical Design Engineer

Sep 2019Oct 2020 · 1 yr 1 mo · Bengaluru, Karnataka

Qualcomm

Physical Design Engineer

Feb 2017Sep 2019 · 2 yrs 7 mos · Bengaluru Area, India

Mindlance technologies

Physical Design Engineer

Jan 2017Sep 2019 · 2 yrs 8 mos · Bengaluru Area, India

Cadence design systems

Product Engineer

Dec 2015Dec 2016 · 1 yr · Bengaluru Area, India

  • Working on Innovus and tempus tool
Innovustempus

Rv-vlsi design center

Physical Design Engineer Trainee

Mar 2015Sep 2015 · 6 mos · Bengaluru Area, India

  • I worked on Physical design of Torpedo block design incorporated with 32 macros, 43000 cell instances and 5 clocks (3 propagated and 2 generated clock) in a die size of 5.9 mm sq, operating at 400 MHz frequency, supply Voltage 1.8v, technology 180nm fab JAZZ semiconductor.
  • I faced some challenges in the project are listed below
  • >During floorplan, the placement of 32 macros by avoiding stacking problem
  • >Create the best power network to meet the IR drop
  • >Fixing floating Pin and floating shape errors
  • > Analyzing timing reports
  • >Found fault in the Design constraint file
  • >Fixed timing violations using Useful Skew during CTS

Grid india it innovations

Internship

Jan 2014Jun 2014 · 5 mos · Bengaluru Area, India

  • Digital design of physical layer used in USB3.0 using Verilog. The physical layer used in USB3.0, with a DC balanced 8B/10B encoding.

Education

BVBCET

Master of Technology (M.Tech.) — VLSI Design & Testing

Jan 2012Jan 2014

Visvesvaraya Technological University

Bachelor of Engineering (BE) — Electronics and Communications Engineering

Jan 2008Jan 2012

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