SAUD M. MOHAMED — Software Engineer

Executive Summary Senior Physical Design Engineer with 6 years of hand on experience in implementing complex SOC’s, GPU’s and Network chips in 45nm, 28nm, 20nm and 16nm technologies. Core Competency • Strong hands on experience in all aspects of IC Design and Implementation including Design Setup, Floor Planning, Power Planning, Placement, Clock Tree Synthesis, Routing, DFM Checks, Parasitic Extraction, Timing Analysis (STA), Signal Integrity (SI) Analysis, Power and IR Drop Analysis, Formal Verification, ECO Implementation and Physical Verification. • Strong hands on experience in physical implementation of several Partitions and Macros with High Timing Performance and Low Power demands. • Strong hands on experience in Low Power Implementation and Good understanding about various Static and Dynamic power reduction techniques. • Good understanding of IC Design concepts, CMOS processes, Latch-up, Antenna, EM and DFM issues. • Good understanding in Static and Dynamic IR Drop analysis and fixes. • Good understanding about Cross talk effects, On Chip Variation (OCV). • Hands on experience in Timing ECO preparation and Timing closure. • Excellent in Physical Verification, DRC, LVS cleanup and DPT fixes. • Proficient in Tcl and Perl scripting. • Worked in 45nm, 28nm, 20nm and 16nm technologies. • Worked in Netlist to GDSII implementation of complex designs varying from 200K to 1.4Million instance count and 200MHz to 1.76GHz clock frequency range. Technical Skills • Place and Route – Synopsys ICC, ICC-II, Cadence Encounter, Innovus, Magma Talus, Mentor Olympus. • Static Timing Analysis- Synopsys Prime Time SI. • Parasitic Extraction – Synopsys StarRC. • IR Drop Analysis – Apache Redhawk. • Power Lint – Cadence Conformal Low Power • ECO Generation – Tweaker. • Physical Verification – Mentor Calibre, Synopsys ICV.

Stackforce AI infers this person is a Senior Physical Design Engineer specializing in VLSI and ASIC design.

Location: Bengaluru, Karnataka, India

Experience: 15 yrs 5 mos