Manish Pillai — Software Engineer
MediaTek leverages my expertise in Static Timing Analysis (STA) and timing closure as I contribute to advanced physical design projects. My role emphasizes precision and collaboration, focusing on delivering optimized semiconductor solutions for complex technology nodes. Pursuing an MTech in VLSI Design at Vellore Institute of Technology, I combine academic rigor with practical experience. With a foundation in RTL design and digital circuits from prior roles, I am driven to advance innovation in the semiconductor industry through continuous learning and impactful contributions.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and digital circuit design.
Location: Bengaluru, Karnataka, India
Experience: 1 yr 7 mos
Skills
- Static Timing Analysis
- Physical Design
- Synthesis
- Timing Analysis
- Rtl Design
- Digital Circuit Design
Career Highlights
- Expert in Static Timing Analysis and timing closure.
- MTech candidate with strong VLSI Design background.
- Proficient in RTL design and digital circuits.
Work Experience
MediaTek
Senior Design Engineer (STA Signoff) (10 mos)
Intern (11 mos)
Entuple Technologies Pvt. Ltd.
Synthesis and Timing Analysis (2 mos)
Tech Mahindra Cerium Pvt Ltd
RTL Design Engineer (9 mos)
Associate Engineer (1 mo)
Indian Oil Corp Limited
Student Intern (1 mo)
Education
Master of Technology - MTech at Vellore Institute of Technology
B.Tech at Federal Institute of Science and Technology (FISAT)
Sr. secondary at Father Agnel School
Higher Secondary at New Sainik Public School
