Rajiv Mittal — CTO
Experienced professional in the field of standing of ASIC Chip Design with the strong understanding of Flows and Methodologies - Physical Design Lead for number of SoCs in Cellular Product Group and Microcontroller Solutions (Automobiles) Group - Expertise in Static Timing Analysis including Delay Noise closure, Synthesis, Formal Verification, Place and Route, Clock Tree Synthesis and CPF based Low Power Flow - Experience across wide range of technologies (5nm to 130nm)
Stackforce AI infers this person is a leader in ASIC Chip Design with a focus on low-power solutions for automotive and cellular industries.
Location: Bengaluru, Karnataka, India
Experience: 25 yrs 3 mos
Career Highlights
- Expertise in ASIC Chip Design and methodologies.
- Led Physical Design for multiple SoCs in key product groups.
- Extensive experience across advanced technology nodes.
Work Experience
LeadSoc Technologies Pvt Ltd
CTO and Head of Engineering (1 yr)
NXP Semiconductors
Senior Director (3 yrs)
Director (1 yr 8 mos)
ALTEN Calsoft Labs
Director (1 yr 9 mos)
Si2chip Technologies Pvt. Ltd.
Director (1 yr 2 mos)
Qualcomm
Principal Engineer (7 mos)
Sr Staff Engineer (3 yrs 5 mos)
AMD
Senior Member Technical Staff (1 yr 7 mos)
Freescale Semiconductor
Staff Design Engineer (11 yrs 1 mo)
Education
BE at Punjab Engineering College