Nikhil Jain — Product Engineer

I am a VLSI enthusiast with a strong foundation in digital logic design, RTL-to-gate-level synthesis, and timing closure methodologies. Currently pursuing M.Tech in VLSI Design at VIT Vellore, with hands-on experience in industry-standard EDA tools (Synopsys Design Compiler, PrimeTime, Cadence Genus). Key Focus Areas: RTL-to-gate synthesis flow & optimization SDC constraint development & analysis Multi-mode multi-corner (MMMC) static timing analysis Hold/setup violation and path delay analysis Clock domain crossing & timing exceptions Passionate about building timing-optimized, power-efficient digital systems. Eager to contribute to real-world tape-outs and add value to ASIC design teams. 📩 Email: nikhil.jain@mediatek.com

Stackforce AI infers this person is a VLSI Design enthusiast with a focus on ASIC development.

Location: Bengaluru, Karnataka, India

Experience: 0 mo