Shubham Patil

Software Engineer

Bengaluru, Karnataka, India7 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expertise in RTL Design and Formal Verification.
  • Proven experience in ASIC and SoC development.
  • Strong background in dynamic and formal verification methodologies.
Stackforce AI infers this person is a highly skilled ASIC Design Engineer specializing in advanced verification and design methodologies.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignFormal Verification

Other Skills

Micro-ArchSTACDC/RDCDynamic VerificationRTL CodingSystem VerilogDesign for debugMicro-Arch developmentLow-power DesignApplication-Specific Integrated Circuits (ASIC)System on a Chip (SoC)JTAGMIPI I3CAMBA AHBSpyglass lint

About

Senior ASIC Design Engineer with expertise in, RTL Design Micro-Arch STA CDC/RDC Formal Verification Dynamic Verification

Experience

7 yrs 9 mos
Total Experience
4 yrs 5 mos
Average Tenure
3 yrs 3 mos
Current Experience

Nvidia

Senior ASIC Design Engineer

Jan 2023 – Present · 3 yrs 3 mos · Bengaluru, Karnataka, India

RTL DesignMicro-ArchSTACDC/RDCFormal VerificationDynamic Verification

Intel corporation

3 roles

Senior RTL Design Engineer

Promoted

Jan 2021 – Jan 2023 · 2 yrs · Bengaluru, Karnataka, India

IP Design Verification Engineer

Apr 2019 – Dec 2020 · 1 yr 8 mos · Bengaluru, Karnataka, India

Intern

Jul 2018 – Apr 2019 · 9 mos · Bengaluru, Karnataka, India

Education

Vellore Institute of Technology

Master of Technology - MTech — Embedded Systems

Aug 2017 – Apr 2019

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