Amol Patil

Software Engineer

Bengaluru, Karnataka, India24 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Digital Logic and Unified Power Format.
  • Proven experience in ARM architecture and X86 server core verification.
  • Strong background in scripting and power management.
Stackforce AI infers this person is a Verification Engineer with expertise in semiconductor and embedded systems.

Contact

LinkedIn

Skills

Core Skills

Unified Power Format (upf)Digital LogicArm Architecture

Other Skills

ScriptingPower ManagementVHDLVerilogProcessorsMicroprocessorsSoCARMDFTFunctional VerificationJTAGSystemVerilogASICFormal VerificationDebugging

About

Result oriented. Good team player. Like to work on cutting edge technologies.

Experience

24 yrs 8 mos
Total Experience
3 yrs 6 mos
Average Tenure
11 yrs 5 mos
Current Experience

Intel corporation

Component Design Engg

Nov 2014 – Present · 11 yrs 5 mos

ScriptingUnified Power Format (UPF)Digital LogicPower Management

Lsi india research & development pvt ltd

Sr. Staff Engg

Mar 2013 – Nov 2014 · 1 yr 8 mos · Pune Area, India

ScriptingUnified Power Format (UPF)Digital LogicPower Management

Appliedmicro

Sr. Staff Engg

Apr 2011 – Mar 2013 · 1 yr 11 mos · Pune

  • ARM V8, 64 bit processor SoC verification and ASM language env development
ScriptingDigital LogicARM Architecture

Amd

Member of Technical Staff

May 2007 – Mar 2011 · 3 yrs 10 mos · Pune Area, India

  • Verification of multimillion gate X86 server cores.
  • Gate level simulations of x86 processor.
  • DFT functional verification. Automated test generator tool development for DFT.
  • Verification of Memory BIST controller.
  • Verification of BIST Memory repair
Digital Logic

Tensilica

Verification Engg

Apr 2006 – May 2007 · 1 yr 1 mo · Pune

  • Verification of Tensilica customizable processor.

Tata consultancy services

Assistant System Engg

Mar 2004 – Apr 2006 · 2 yrs 1 mo · Pune Area, India

  • Verification of MIPS processor Core. Worked on H/W & S/W co simulation.
  • Requirement Capture & Analysis (formal verification of these requirements)

Cg-corel logic systems

Design Engg

Jul 2001 – Mar 2004 · 2 yrs 8 mos · Pune Area, India

  • Digital system design using FPGA, CPLD, Microprocessor, Micro controller & associated peripheral.
  • RTL coding, IP core development & Simulation for System on Chip (SOC) & FPGAs. Firmware development in C & C++ for Micro controllers & Micro processors; Card level debugging using JTAG & Logic Analyser (Agilents’

Education

COEP Pune

M.Tech — E&Tc

Jan 2003 – Jan 2005

SES college of engg Dhule

BE — E&Tc

Jan 1995 – Jan 2000

Maratha Highschool, Nashik

Under Grad — Science

Jan 1988 – Jan 1994

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