Revanth kumar Mareedu

Software Engineer

Bengaluru, Karnataka, India0 mo experience

Key Highlights

Expert in DFT solutions for semiconductor technologies.
Proficient in digital design and verification methodologies.
Strong collaboration skills with design teams.

Stackforce AI infers this person is a DFT Engineer specializing in semiconductor design and testability.

Contact

Skills

Core Skills

DftDigital DesignTestability Analysis

Other Skills

Automatic Test Pattern Generation (ATPG)Scan InsertionBISTMqttC (Programming Language)ArduinoSynopsys toolsScan compressionBoundary ScanJoint Test Action Group (JTAG)

About

As a seasoned DFT Engineer, I design and implement testable digital circuits, ensuring high quality and reliability in complex systems. I develop and optimize test patterns, collaborate with design teams, and utilize industry-standard tools and methodologies (e.g., Synopsys, Mentor Graphics, IEEE 1149.1). With expertise in digital design and verification (Verilog, VHDL, SystemVerilog), test pattern generation, and fault simulation, I stay up to date with emerging trends and technologies in testability and reliability, delivering successful projects and driving innovation in the field.

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Mediatek

DFT Junior Engineer

Mar 2025 – Present · 1 yr 1 mo · Bengaluru, Karnataka, India · On-site

I am thrilled to announce that I have started a new role as a DFT Junior Engineer at MediaTek! 🎉
In this position, I will be working on designing, implementing, and verifying the Digital Front-End (DFT) solutions, contributing to the development of innovative semiconductor technologies. I am looking forward to expanding my skills, collaborating with talented engineers, and making a positive impact on the company's cutting-edge products.
Thank you to everyone who has supported me along the way,I'm eager to begin this new chapter and contribute to MediaTek's mission of advancing connectivity and technology!

Automatic Test Pattern Generation (ATPG)Scan InsertionDFTDigital Design

Chipedge technologies pvt ltd

DFT Trainee

May 2024 – Oct 2024 · 5 mos · Bengaluru, Karnataka, India · On-site

As a DFT (Design for Testability) trainee at ChipEdge Technologies, I am embarking on a journey to master the art of designing testable digital circuits. My training is focused on acquiring in-depth knowledge of DFT concepts, methodologies, and tools, enabling me to implement efficient test solutions for complex semiconductor designs.
I am eager to apply my skills in scan chain implementation, JTAG protocol, and testability analysis to contribute to the development of high-quality, reliable chips. Through collaboration with experienced design teams, I aim to enhance my expertise and stay up-to-date with industry trends and advancements in DFT. Let's connect and explore opportunities in the fascinating world of semiconductor design and testability!

BISTScan InsertionDFTTestability Analysis