Raj Tanti

Software Engineer

Bengaluru, Karnataka, India4 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in DFT methodologies and ATPG techniques.
Proficient in advanced simulation tools for semiconductor design.
Experience with cutting-edge 3nm and 4nm technology.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in DFT and advanced testing methodologies.

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Skills

Core Skills

Dft

Other Skills

SSNATPGGate level SimulationDebuggingBoundary ScanIJTAGLinuxSimulationJoint Test Action Group (JTAG)Scan InsertionMBISTAutomatic Test Pattern Generation (ATPG)VerilogVery-Large-Scale Integration (VLSI)

About

Worked on Scan-insertion, Automatic Test Pattern Genaration (ATPG), Scan-Compression, EDT, CODEC, Gate level simulation, ATPG DRCs, Debug test-coverage and also debug simulation mismatches, development of testbench for RTL and build TCL files and C-Shell files to automate existing ATPG flow suitable for Tessent Shell. Worked on EDT tools like Tessent Shell, TestKompress, Synopsys VCS, Verdi, Xcelium Cadence, DVE. Worked on 4nm and 3nm technology on SoC with SSN based architecture.

Experience

4 yrs 11 mos

Total Experience

2 yrs 5 mos

Average Tenure

3 yrs 5 mos

Current Experience

Mediatek

2 roles

Senior Engineer (DFT)

Mar 2026 – Present · 1 mo · Bengaluru, Karnataka, India · On-site

DFT Engineer (on-contract)

Nov 2022 – Mar 2026 · 3 yrs 4 mos · Bengaluru, Karnataka, India · On-site

Test coverage enhancement.
Performed ATPG on various fault model like Stuck-at, Transition, RAM-sequencial, IDDQ, SDD, Bridge, Cell-Aware and Retention. (Tessent)
Performed Gate level Simulation and debug the Mismatches such as fault models like stuck-at, transition delay, RAM-sequencia and retention test. (VCS, Xcelium, Verdi).
Also performed min-delay, max-delay and no-delay Simulation and debug the timing mismatch.
Done the Retarget also of the stuck-at fault, transition delay fault and RAM-sequencial fault. And done the no-delay, min-delay and max-delay simulation on that on chip-top level.

DFTSSN