Bijoy Gopal Nandy

Software Engineer

Bengaluru, Karnataka, India19 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in low-power design for complex SoCs
Developed tools reducing UPF rejections by 95%
Strong collaboration with DV teams for power-aware solutions

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in low-power methodologies and VLSI CAD engineering.

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Skills

Core Skills

Low-power DesignSystem On A Chip (soc)

Other Skills

Leakage PowerSoC Usecase AnalysisCLPTcl-TkC++Perl AutomationSoftware DevelopmentEDATCLPerl ScriptUnix Shell ScriptingVHDLC/C++ STLData StructuresPerl

About

As a Senior Staff Engineer at Qualcomm with nearly a decade of experience, I specialize in low-power design and UPF quality checks for complex SoCs. My role focuses on delivering SoC power architecture specifications, enabling verification and implementation teams, and optimizing pre- and post-silicon power estimation and correlation processes to meet project requirements. At Qualcomm, I led the creation of a comprehensive UPF quality check tool that significantly reduced UPF rejections and design handoff iterations. My work ensures efficiency and precision in low power methodology while driving innovation in VLSI CAD engineering. Passionate about delivering cutting-edge solutions, I aim to advance Qualcomm's leadership in semiconductor design.

Experience

19 yrs 10 mos

Total Experience

6 yrs 7 mos

Average Tenure

10 yrs 11 mos

Current Experience

Qualcomm

Senior Staff Engineer

Jun 2015 – Present · 10 yrs 11 mos · Bengaluru, Karnataka, India

Die Power Lead for multiple SoCs
o SoC Power Arch spec closure based on project requirement.
o Low Power design delivered for top level IPs and complete design to enable DV and Implementation
o Estimate the pre silicon power for different usecases and work on corelation in Post Silicon.
o Experienced in working different
. UPF Quality Check ( UPFQC )
o Comprehensive checks to catch know UPF issues upfront to reduce design to DV and PD handoff iterations of UPF.
o Differential UPF feature can compare and report the differences between two flavours of UPF.
o Along with other low power checks the flow can check for CSN issues and generates the missing CSNs.
o 95% reduction in UPF Rejection, 81% reduction in UPF related design CR- achieved on time PARTL & PAGLS bringup.
End2end Retention Consistency
o The solution verifies that the retention intent of each cores and top at RTL level is consistent with SoC implementation level retention. The flow verifies pre-Tiled RTL retention to post-Tiled RTL retention, post-Tiled retention to implementation level retention.
PA RTL/GLS Enablement
o Provided dedicated support to fix all power aware bringup issues like DB mismatch, Object not found, DB inside DB
o Achieved timely power aware simulation enablement and zero rejection through power intent quality checker solution developed using VCLP APIs.
o Strong collaboration with DV team to debug and fix low power test failure.
Low Power Dashboard
o One stop solution to get UPF status for all core and SoCs at any point of time for any release tag. It capture the status of PIE, DV, CLP, Synthesis & UPFQC.