May 2017 – Mar 2020 · 2 yrs 10 mos · Bengaluru, Karnataka, India

• Handled multiple projects of low power design in multiple technologies (5lpp, 7ff, 8lpp, 11lpp)
• Handled many multimillion subsystems having multiple power domains (switchable and always on), high congestion, thousands of Feedthroughs (FTs), hundreds of clocks, many PLLs and RCGs, thousands of retention registers, many PMUXs, thousands of level-shifters and isolation cells
• Reduced work complexity by writing various scripts
• Implemented island buffering for overall area saving and reducing congestion
• Implemented OCC
• Successful closer of all the blocks with high utilization target with on time tapeout

Jun 2013 – May 2017 · 3 yrs 11 mos · Bengaluru, Karnataka, India

• Implemented many designs in multiple projects with successful tapeouts of high-speed multi-million digital SoC in 16 and 28nm technology
• Major contributor in timely tapeout of 16nm chip after complete closer of a most critical and sensitive block assigned at a very critical point of the project
• Reduced the power by a significant amount of a multi instantiated design, hence reduced over all chip power
• Implemented a highly congested block where crosstalk was the major issue
• Reduced work complexity by writing various scripts