Vikas Bhandari

CTO

Bengaluru, Karnataka, India15 yrs 7 mos experience

Most Likely To SwitchAI ML Practitioner

Key Highlights

Led cross-functional teams for chip verification.
Expert in CPU and interconnect design.
Innovative approaches to verification recognized as trade secrets.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in CPU and interconnect design.

Contact

Skills

Core Skills

Computer ArchitectureFormal VerificationSystem Verilog

Other Skills

CC++Project ManagementArtificial Intelligence (AI)Python (Programming Language)AMBAUVMVerilogMicroprocessorsVLSIPHPMatlabHTMLMySQLSEO

About

13+ years of Experience in CPU,interconnect Design and Verification. Led cross functional Design and Verification teams for multiple chips. Currently working on Agentic AI development for hardware products and driving unit, subsystem and soc verification at Nvidia focusing on formal and DV. Experience in working with teams across multiple geographies (EMEA, APAC and NA) regions. Worked on top level Verification for A class core (A75) comprising of v8+ architecture. Worked on Qualcomm Centriq series of chips for datacenter market. Involved in verification of Processor subsystem involving multiple CPUs, L3s and high end interconnect. Worked on Processors targeting Automotive, IoT, Datacenters and Mobile markets. Experience in both ARM as well as ARC Architectures. Expert level Knowledge in Computer Architecture, UVM, SV,C,C++, Perl. My research interest includes cache coherency, High speed interconnects, super scalar architectures and asynchronous processor architectures.

Experience

15 yrs 7 mos

Total Experience

2 yrs 1 mo

Average Tenure

7 yrs 10 mos

Current Experience

Nvidia

ASIC Verification Engineering Lead

Jul 2018 – Present · 7 yrs 10 mos · Bengaluru Area, India · Hybrid

CPU/Interconnect/SoC verification using DV and FV.
Team Lead for multiple unit level TBs related to CPU, interconnect and SoC verification.
Driving multiple unit Level TBs development, AI agent developement, architecture and formal verification.
Working on Unit level, Integration Level and Bring up efforts for Nvidia next generation chips.
Leading multiple teams across sites to verify multiple unit level IPs, CPU and SoCV using DV and Formal.

Computer ArchitectureCC++Formal VerificationProject ManagementArtificial Intelligence (AI)+4

Qualcomm

Senior Engineer

Nov 2016 – Jul 2018 · 1 yr 8 mos · Noida Area, India

Worked on verifying one of the most innovative product of Qualcomm. Part of the R&D team in India working on Qualcomm ARM based server chips focusing on CPU, Caches and high end interconnect verification.
Received 4 Qualstars (Highest in India) for the exceptional work done in server verification.
Developed configurable test bench agents and environment for the processor subsystem.
Developed novel approach to verify huge set of registers in the chip.
IDF filed for one of the novel approaches developed for verification. Accepted as a trade secret in Qualcomm.
Worked on interconnect verification involving multiple CPUs and High level caches.
Verification lead for the debug verification at the processor subsystem.
Mentored and trained new hires, experienced folks on Qualcomm flow and verification.

Computer ArchitectureCC++System VerilogPython (Programming Language)AMBA+1

Arm

Verification Engineer

Nov 2015 – Nov 2016 · 1 yr · Bengaluru Area, India

Worked on CPU Verification and cache coherency on ARM A75 core.
Worked on Verification of A75 and did verification of dside on multi-cpu configurations.
Verified various sync-up scenarios, DoS scenarios, True sharing and False sharing scenarios as part of cache coherency verification.
Worked on external interfaces and verified the cache coherency, AMBA4 and AMBA5 on the processor design.
Worked on verifying ECC logic on various level of caches in A75 core.
Implemented flow to collect coverage statistics to improve coherency tests and RIS tools.
Worked on external ACP and snoop interfaces of the processor design.

Computer ArchitectureCC++System VerilogPython (Programming Language)AMBA+1

Synopsys

2 roles

R&D Engineer II

Promoted

Jun 2014 – Oct 2015 · 1 yr 4 mos · Hyderabad Area, India

Did Design, Verification (Module Level, Top Level), Benchmarking, Synthesis and Formal Verification on wide range of Processor cores by ARC Synopsys.
Involved with Verification of ARC 600, ARC 700 and ARC EM cores.
Developed Module Level Verification environments, Top level verification environments and Instruction set generators for ARC cores.
Did Design of new Pipeline in EM5D and EM7D products.
Did Design and lead the verification team for the new added uDMA controller in EM9D and EM11D cores.
Did Verification for ECC and Parity support on CCMs for EM.

Computer ArchitectureCC++System VerilogPython (Programming Language)AMBA+1

R&D Engineer I

Jun 2012 – May 2014 · 1 yr 11 mos · Hyderabad Area, India

Worked on ARC Processor Design and Verification.
Did Memory sub-sytems Verification for AHB,AHB-LIte,AXI and APB protocols for the load stores units across ARC 600, ARC700 and ARC EM cores.
Developed self checking assembly codes to verify ARCv1 ISA.
Worked on Random Instruction generator development for ARC Cores.

Computer ArchitectureCC++System VerilogPython (Programming Language)AMBA+1

Cisco systems

Project Intern (SRTG Division)

Jul 2011 – Dec 2011 · 5 mos · Bengaluru Area, India

Developed a web based fingerprint login system which enables the user to login to the router upon the swipe of their finger on the scanner present on the laptops.
Developed a RFP Sheet generation online tool for the Marketing team at Cisco.

Gadgetronica

Co Founder

Jan 2011 – Jun 2012 · 1 yr 5 mos

Gadgetronica is a one-stop destination for all tech-news. The site carries the latest news from various quarters like social media, new gadgets, new technology, product specifications and reviews. Founded in 2011, Gadgetronica is committed to serving as a reliable and up-to-date source of information for the layman and techno-geeks alike.