Deepthi Dasari

Director of Engineering

San Jose, California, United States19 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in SoC and CPU verification methodologies.
Proven leadership in team building and mentorship.
Extensive experience with emulatable transactors and test benches.

Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on SoC and CPU architectures.

Contact

Skills

Core Skills

Soc VerificationPcie VerificationDesign VerificationMemory Hierarchy VerificationVerificationCache Coherency VerificationPower ManagementCpu VerificationArchitecture ValidationAsic VerificationSoc Validation

Other Skills

Emulatable transactorsTest benchesTeam buildingMentorshipCross-site interactionsMemory Hierarchy Testbench OwnershipPower management verificationPost-Silicon ValidationPERL scriptingValidation of SoCModule Level VerificationFormal VerificationVerilogVHDLAssembly Language

About

Specialties: Programming/Scripting Languages: Verilog, VHDL, Assembly Language, C, C++, PERL, SQL, HTML, Java Script. Verification Languages: System Verilog, e language, Property Specific Language (PSL)–Formal Verification. Tools: Modelsim, NCsim, VCS, Specman, Questasim, Verdi, Debussy, Intel Internal Architecture Simulator Tools, Denali pureview, P-Spice, Xilinx, Design Compiler, PrimeTime, Matlab

Experience

19 yrs 8 mos

Total Experience

4 yrs 10 mos

Average Tenure

4 mos

Current Experience

Rivos inc.

SoC Verification

Nov 2021 – Jan 2026 · 4 yrs 2 mos

Lead various DV efforts
> Development of Emulatable transactors and test benches across all major interfaces in SoC.
> PCIE Verification at IP, Subsystem and SoC
> SoC Verification focussing on Core, Coherent Fabric, PCIE and Memory paths
> Team building and mentorship

Emulatable transactorsTest benchesPCIE VerificationSoC VerificationTeam buildingMentorship

Apple

3 roles

Design Verification Manager

Promoted

Oct 2018 – Oct 2021 · 3 yrs

Managing Transactors and Test benches team
Responsible for Emulatable Transactors development
Test bench Ownership and Verification of Memory Hierarchy across SoC
Cross-site interactions with Israel and Cupertino teams
Emulation based verification of memory hierarchy and cache coherency
Team building and mentorship

Emulatable TransactorsTest benchesMemory Hierarchy VerificationCross-site interactionsDesign Verification

Verification Lead

Oct 2014 – Oct 2018 · 4 yrs

Responsible for development of Emulatable transactors for CPU and Fabric interfaces
Cache Coherency Verification
Memory Hierarchy Testbench Ownership
Team Building and Mentorship

Emulatable transactorsCache Coherency VerificationMemory Hierarchy Testbench OwnershipVerification

CPU Verification Engineer

May 2011 – Oct 2014 · 3 yrs 5 mos

Power management verification
Cache coherency verification
Development of emulatable transactors for CPU <-> Cache interfaces
Stimulus generator development for coherency testing

Power management verificationCache coherency verificationEmulatable transactorsVerificationPower Management

Intel corporation

CPU Verification Engineer

May 2009 – May 2011 · 2 yrs

Architecture Validation of next generation multi-core CPU:
o Trained on IA-32, IA-64 architectures, P6 microarchitecture, Memory Hierarchy, Multi Level Caches, Cache Coherency, Intel internal architecture simulator tools and verification environment
o Reset Validation of multi-core CPU at Full Chip Level.
o Generation of tests targeting Multi-Core, Multi-threaded functionality using Intel’s internal native instruction test generator tools.
o Development of test plan and generation of tests targeting the new instructions supported by the processor.
o Ownership of Full Chip regressions, Debug and triage of failing Full Chip test cases in Architecture Simulator based co-simulation environment to find RTL failures/ Architecture Simulator issues.
o PERL scripting for Post-processing of Full Chip regression results.
Post-Silicon Validation of next generation multi-core CPU:
o Addressing speed issues by identification of speed-paths in the design.
o Fault Isolation and Analysis of Vmin failures and Scan chain/Capture failures.
o Stop clock validation using Test Access Port features.

Architecture ValidationPost-Silicon ValidationPERL scriptingCPU Verification

Texas instruments

ASIC Verification Engineer

Jul 2006 – Apr 2009 · 2 yrs 9 mos

Project I - Single Chip baseband 3G solution for NOKIA
o Responsible for validation of SoC using ‘C’ testcases and co-simulation environment of TI.
o Module Level Verification of PSCON(Power State CONtroller) module
 Test Plan Writing and Functional/Code Coverage
 System Verilog based test stimulus generator
 Formal Verification using PSL (Property Specific Language)
o Validation of G12 module (Image Processor) using C testcases.
o Power Aware setup and simulations at RTL and GATE level using Modelsim.
Project II - Connectivity SOC project for NOKIA (Bluetooth, FM, GPS)
o Gate Level validation using C and e testcases.
o Power Aware simulations using Modelsim