Sarthak Grover

Product Engineer

Bengaluru, Karnataka, India9 mos experience

Key Highlights

Expert in complete RTL-GDS flow management.
Hands-on experience with industry-standard EDA tools.
Strong foundation in semiconductor design and innovation.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and RTL-GDS flow.

Contact

Skills

Core Skills

Physical Design

Other Skills

InnovusPrimetimeTiming ClosureDRC FixingStatic Timing AnalysisPlace & RouteDRC ClosureRTL DesignLogic DesignDesign Rule Checking (DRC)Layout Versus Schematic (LVS)Digital Circuit DesignEquivalence CheckingDFTLTSpice

About

"Man is defined only by his actions." ~Jean-Paul Sartre, Existentialism is a Humanism Pursuing Electronics and VLSI at IIIT Delhi was a defining action—one that shaped my passion for semiconductor design. My journey has been driven by curiosity and hands-on experience, from designing a custom OAI33 complex logic gate to developing a Cortex-M0-based sleep tracker SoC. Working with industry-standard tools like Cadence Virtuoso, Innovus, and Genus, I focus on bridging design and innovation in hardware. With a strong foundation in RTL design and problem-solving, I am always exploring new challenges in semiconductor. Let’s connect and innovate together!

Experience

9 mos

Total Experience

8 mos

Average Tenure

8 mos

Current Experience

Mediatek

Physical Design Engineer

Sep 2025 – Present · 8 mos · Bengaluru, Karnataka, India · On-site

I am currently engaged in a time-based contract on an SoC project with MediaTek, where I manage the complete physical design flow for multiple blocks. My responsibilities include floorplanning, congestion analysis and optimization, timing closure, DRC fixing, verification, and clock tree synthesis (CTS) optimization.
I also focus on resolving flow-related issues, improving implementation efficiency, and ensuring clean, sign-off-ready designs that meet project timelines and quality standards.

InnovusPrimetimePhysical Design

Leadsoc technologies pvt ltd

Physical Design Engineer

Aug 2025 – Present · 9 mos · Bengaluru, Karnataka, India · On-site

I work closely with clients on end-to-end Physical Design (PD) projects, driving implementation from floorplanning through sign-off. My experience spans floorplanning, Place & Route (PnR), RC extraction, Static Timing Analysis (STA), IR drop analysis, DRC closure, and schematic-to-layout verification.
With in-depth knowledge of the complete RTL-to-GDSII flow, I help optimize design methodologies to achieve the best possible PPA (Power, Performance, and Area). I focus on improving flow efficiency, accelerating debug cycles, and ensuring smooth project execution.
I have strong hands-on expertise with Cadence Innovus, leveraging its capabilities to deliver robust, timing-closed, and sign-off-ready designs within tight schedules.

Physical DesignStatic Timing Analysis