sai chandu gali

Software Engineer

Bengaluru, Karnataka, India7 yrs 9 mos experience

Key Highlights

7+ years of experience in VLSI industry.
Expert in low power design and multi voltage domain blocks.
Proficient in handling high instance count and frequency blocks.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Low-power methodologies.

Contact

Skills

Core Skills

Physical DesignLow-power Design

Other Skills

Static Timing AnalysisPlace and routeLowpowerFull chipPhysical VerificationPlace & RouteVery-Large-Scale Integration (VLSI)LinuxC (Programming Language)PerlTCLFloorplanningSynopsys PrimetimeClock Tree SynthesisCadence Encounter

About

Physical Design Engineer with an 7+ years of experience in the VLSI Industry. Worked on blocks from RTL to GDSII, good in floorplaning, place and route, STA. Handled the blocks with high inst count and freq. Expertise in handled the low power design and multi voltage domain blocks Done various projects in lower technology nodes. Additional skills Scripting in TCL-TK, UNIX and PERL. Worked in Flow development for lower technologies. Exposure in EDA tools in Cadence and Synopsys.

Experience

7 yrs 9 mos

Total Experience

1 yr 3 mos

Average Tenure

1 yr 2 mos

Current Experience

Broadcom

R&D IC Design Engineer

Feb 2025 – Present · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

Amd

Senior silicon design engineer

May 2024 – Feb 2025 · 9 mos · Bengaluru, Karnataka, India · Hybrid

complete PD execution of multiple IP's from synthesis to GDS.

Mediatek

Senior Physical Design Engineer

Jan 2022 – May 2024 · 2 yrs 4 mos · Bengaluru, Karnataka, India · On-site

worked on lower tech nodes. like 22nm,7nm,6nm and 4nm.
ownership for blocks from Place to GDS flow.

Static Timing AnalysisPlace and routeLowpowerPhysical DesignLow-power Design

Invecas

Physical Design Engineer 2

Dec 2020 – Dec 2021 · 1 yr · Hyderabad, Telangana, India

Soctronics

Physical Design Engineer 1

Nov 2018 – Nov 2020 · 2 yrs · hyderabad ,telangana

Veda iit

intern at veda iit

May 2018 – Nov 2018 · 6 mos

Trained as physical design engineer with the complete exposure on RTL-GDSII.

Education

MVSR Engineering College

Bachelor of Engineering - BE — electronics and communication engineering

Jan 2014 – Jan 2018

Sri sai grammer high school

SSC — High School

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