D

Dillip Badu

Software Engineer

Bengaluru, Karnataka, India14 yrs 10 mos experience
Highly Stable

Key Highlights

  • 14+ years in semiconductor industry
  • Expert in EDA and design evaluation
  • Proven track record in technology innovation
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in EDA methodologies and advanced node technologies.

Contact

Skills

Core Skills

InnovusPpa OptimizationDesign Flow DevelopmentMentorshipAdvanced Node Flow TestingMetrics CreationProduction Issue SupportSolution Delivery

Other Skills

Clock Tree SynthesisFloorplanningCAD MethodologyFusion compilerPlace and RouteVerificationPNR methodologyAdvance nodeCTSLow-power DesignPhysical DesignStatic Timing AnalysisCadenceASICVLSI

About

With over 14+ years in the semiconductor industry as an EDA engineer specializing in Flow, Methodology, and design evaluation, I drive technology innovation, ensure customer success, and achieve business growth. I am a results-oriented problem solver who guides teams to develop robust solutions and champions customer satisfaction, and I am a collaborative professional experienced in both large corporate and start-up environments. Specialties: *Innovus, CAD, and low-power design, enhancing design efficiency and addressing technology gaps. *Collaborates with teams to advance methodologies for cutting-edge semiconductor design. *End-to-end customer flow ideation, product planning, and execution. *Exceptional communication skills (written, verbal, and presentation). *Adept at navigating ambiguity and managing change. *Mentored junior engineers and developed training modules to cultivate in-house talent. *Managed design implementations, including customer interaction and issue tracking. *Developed strong process and organizational maturity through extensive customer engagement. ENGINEERING: *ASIC Physical Design of multi-million gate SOCs and high-frequency, power-hungry IP cores (netlist to GDS). Implementation in advanced technology nodes (e.g., n3e, n2p). *Reference Methodology development to implement signoff flows, accelerating Turnaround Time (TAT). *P&R Product development and validation.

Experience

14 yrs 10 mos
Total Experience
3 yrs 9 mos
Average Tenure
3 yrs 5 mos
Current Experience

Cadence

2 roles

Senior Principal Application Engineer

Promoted

Dec 2025Present · 4 mos · Bengaluru, Karnataka, India

Principal Application Engineer

Nov 2022Dec 2025 · 3 yrs 1 mo · Bengaluru, Karnataka, India

  • 1.Leadership in Advanced Process Node Development: Drove the complete development and precise floorplanning of N3/N2 process flows. This ensured peak performance and manufacturability for a key client's next-generation silicon.
  • 2.GPU PPA Optimization and CAD Methodology Advancement:Optimized GPU Power, Performance, and Area (PPA) significantly through innovative design techniques and concurrent methodologies, leading to enhanced efficiency and design cycles.
  • 3.Power Grid Design and Implementation Expertise: Established, documented, and rigorously implemented comprehensive power grid (PG) guidelines and methodologies, ensuring robust power delivery and signal integrity across complex designs.
  • 4.Strategic PPA Improvement Initiatives: Proactively identified and executed strategic Power, Performance, and Area (PPA) improvements, directly contributing to enhanced product competitiveness and market differentiation.
  • 5.Cross-Functional Collaboration for R&D Innovation: Collaborated extensively with Application Engineers (AE) and Product Engineers (PE) to define, validate, and successfully deploy cutting-edge R&D features, driving product innovation and market leadership.
InnovusClock Tree SynthesisPPA Optimization

Intel corporation

SoC Design Engineer

Apr 2019Nov 2022 · 3 yrs 7 mos · bangalore

  • Led Cadence flow development, mentoring four engineers, overseeing projects, ensuring best practices, and optimizing team performance.
  • Developed a comprehensive Place and Route (P&R) design flow, significantly enhancing design efficiency and consistency through clear guidelines, robust verification, and automation.
  • Collaborated with external vendors and foundries to proactively address technology and flow gaps for advanced process nodes, leading technical reviews, problem-solving, and implementing innovative solutions for successful tape-outs.
Fusion compilerInnovusDesign Flow DevelopmentMentorship

Qualcomm

Senior Lead Engineer

Jul 2018Apr 2019 · 9 mos · Bengaluru, Karnataka, India

  • part of advance node enablement team.
  • responsible for advance node flow testing and enhnacement.
  • Responsible for creating qor metrics and checkers to validate the flow from floorplan to pnr and signoff.
  • worked on different platform from earlier experience like synopsys tools suit.
Fusion compilerInnovusAdvanced Node Flow TestingMetrics Creation

Cadence design systems

senior/Lead Application Engineer

Jun 2011Jul 2018 · 7 yrs 1 mo · Bengaluru Area, India

  • Supported production issue in latest node physical design and responsible for creating solution and article.
  • individual contributor towards delivering solution in floorplaning and pnr issue .
InnovusProduction Issue SupportSolution Delivery

Education

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech — microelectronics

Jan 2016Jan 2018

National Institute of Science and Technology (Autonomous, NBA and NAAC Accredited)

B.Tech. — Electronics & Communication Engineering

Jan 2007Jan 2011

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