RACHITA SHEKHAR

Software Engineer

Bengaluru, Karnataka, India4 yrs 5 mos experience

Highly Stable

Key Highlights

Expert in Conformal LEC and digital circuit design.
Strong background in project management and problem-solving.
Master's degree in VLSI from a prestigious institution.

Stackforce AI infers this person is a VLSI and ASIC design expert with strong technical support capabilities.

Contact

Skills

Core Skills

Conformal LecDigital Circuit Design

Other Skills

CMOSAltera QuartusCadence VirtuosoSynopsys toolsVerilogbasics of perlbasics of TCLPhysical DesignApplication-Specific Integrated Circuits (ASIC)Logic SynthesisLow-power Designstatis timing analysisDFTVery-Large-Scale Integration (VLSI)

About

At Cadence Design Systems, our dedication to digital circuit design and application-specific integrated circuits (ASIC) propels the industry forward. My Master of Technology in VLSI from Vellore Institute of Technology underpins our team's commitment to innovation and precision. The structural engineering solutions we develop are informed by my tenure as a Design Engineer at Intel Corporation, where I honed my problem-solving skills and project management. Our goal is to convert challenges into pathways for robust and efficient design outcomes, leveraging our collective technical acumen and strategic insight.

Experience

4 yrs 5 mos

Total Experience

2 yrs 1 mo

Average Tenure

9 mos

Current Experience

Eteros technologies

Design Engineer

Aug 2025 – Present · 9 mos · Bangalore Urban, Karnataka, India · On-site

Cadence design systems

Sr.Application Engineer

Dec 2022 – Mar 2026 · 3 yrs 3 mos · Bengaluru, Karnataka, India · On-site

Provide expert-level technical support to clients, diagnosing and resolving complex Conformal LEC issues such as NEQs related to modelling and optimization in synthesis flow, true NEQs in the tool which enhance the tool quality, runtime issues and aborts.
Collaborate with R&D and PE teams to address tool improvements, ensuring high-quality client deliverables.
Traine clients on best practices for Conformal LEC tools to maximize design and validation effectiveness.

CMOSConformal LEC

Intel corporation

Structural Design Engineer

Jan 2021 – Jan 2022 · 1 yr · Bengaluru, Karnataka, India

Conducted manual and conformal ECO for backend team at Intel Corporation, Bengaluru, India.
Debugged errors using Conformal LEC and handled low power LEC debug efficiently.
Managed multiple projects, learned Functional Equivalence Verification, and performed audit and duet checks.

Conformal LECDigital Circuit Design