Sagiri Venkatasai

Software Engineer

Bangalore, Andhra Pradesh, India7 yrs 3 mos experience

Key Highlights

Experienced in silicon design and verification.
Proficient in DFT methodologies and tools.
Strong background in high-speed SERDES design.

Stackforce AI infers this person is a Silicon Design Engineer with expertise in DFT methodologies and verification in the semiconductor industry.

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Skills

Other Skills

Cadence VirtuosoCadence GenusAltera QuartusModelSimSynopsys goldtimeConformal LECNCSIM

About

Intern at Microsemi, Banglore...

Experience

7 yrs 3 mos

Total Experience

1 yr 9 mos

Average Tenure

1 yr 10 mos

Current Experience

Amd

3 roles

Senior Silicon Design Engineer

Jul 2024 – Present · 1 yr 10 mos · Bengaluru, Karnataka, India

Senior Silicon Design Engineer

Promoted

Jul 2024 – Present · 1 yr 10 mos · Bengaluru, Karnataka, India

silicon design engineer 2

Jan 2020 – Sep 2022 · 2 yrs 8 mos · bangalore

working in SOC DFT DV team.

Intel corporation

2 roles

DFT Verification Engineer

Sep 2022 – Jul 2024 · 1 yr 10 mos · Penang, Malaysia

DFT verification Engineer

Sep 2022 – May 2024 · 1 yr 8 mos · Penang, Malaysia

Cadence design systems

Design engineer - II in High speed serdes team

Feb 2019 – Jan 2020 · 11 mos · India

Microsemi corporation

Synthesis and DFT methodology intern

Apr 2018 – Jan 2019 · 9 mos · Bangalore

As an intern, I had worked on the following areas:
Synthesis, DFT linting, scan stitching, insertion of FLLs, insertion of ioblland gates, serial test, interconnect test, verification of LLs, verification of scan chains, LEC (Logical equivalence check)...