Srinivasan Srinath

Software Engineer

Bengaluru, Karnataka, India27 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

11 years in high-speed circuit design.
Expertise in memory architectures and low-power design.
Led teams in deep sub micron processes.

Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in circuit design and memory architectures.

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Skills

Core Skills

Leadership DevelopmentStrategic PlanningMemory DesignCircuit DesignDeep Sub Micron ProcessesTechnical LeadershipHigh-density Cache DesignTiming ClosureFunctional VerificationCharacterizationPhysical Design

Other Skills

Director levelPlatform DevelopmentQuality AssuranceRisk ManagementSix SigmaMicroprocessorsICRomMemory TestLow-power DesignDebuggingVerilogMachine LearningSemiconductorsASIC

About

• 11 years of experience in high-speed/low-power circuit design spanning multiple memory architectures and generic circuits in five technology generations. • Broad knowledge of high-speed circuit design, development and verification of circuits from software functional specification through tapeout and silicon debug support. • 4 years of experience leading development team from concept to delivery in deep sub micron processes. Specialties: - Memory architectures including SRAM, ROM, CAM, register files. - Set methodology/guideline standards

Experience

27 yrs 2 mos

Total Experience

5 yrs 6 mos

Average Tenure

16 yrs 2 mos

Current Experience

Arm

2 roles

Senior Principal Engineer

Promoted

Oct 2017 – Present · 8 yrs 7 mos

Director levelPlatform DevelopmentLeadership DevelopmentStrategic Planning

Principal Engineer

Mar 2010 – Present · 16 yrs 2 mos

Architect: Drive PPA for memory compilers in Physical IP Group

Memory DesignCircuit Design

Amd

Staff Engineer

Jul 2005 – Oct 2010 · 5 yrs 3 mos

• Technical lead for projects in deep sub micron processes.

Deep Sub Micron ProcessesTechnical Leadership

Sun microsystems

Senior Engineer/MTS

Jul 2000 – Jul 2005 · 5 yrs

Design, implementation, timing closure of high-density caches, complex custom and standard cell/data path circuits, memory characterization.
Driven the evolution of the timing characterization tool in coordination with the internal CAD team and external vendor.

High-Density Cache DesignTiming Closure

Altera

Advanced Engineer

Jul 1999 – Jun 2000 · 11 mos

Functional verification and characterization of circuits for CPLDs and their associated peripheral circuits viz. PLL, LVDS for the APEX – E product line.
BIST for FPGAs.

Functional VerificationCharacterization

National semiconductor

VLSI Design Engineer

Feb 1999 – Jul 1999 · 5 mos

• Designed circuits for standard cell, dynamic, static, macro libraries as a part of the Physical Design Unit team of the M3ii integrated microprocessor.

Circuit DesignPhysical Design