Oct 2013 – Sep 2017 · 3 yrs 11 mos · Greater Hyderabad Area

• Worked on Serdes Verification of 10G/12G/16G/25G for various consumer and Enterprise products
• DPALT/USB PHY verification
• Involved in Testchip Verification

Apr 2012 – Sep 2013 · 1 yr 5 mos · bangalore

• Worked for various clients sankhya labs,LSI, synopsys in bangalore
• Developed UVM testbenches and SystemVerilog golden models
• Worked on USB2.0/USB3.0 coverage

Jul 2011 – Mar 2012 · 8 mos

• Verification of MIPI CSI-2 Receiver Controller
• The Camera Serial Interface 2 defines an interface between a peripheral device (camera) and a host processor (baseband, application engine) for mobile applications.The CSI-2 receiver has Receiver PHY layer, CSI-2 receiver controller (multi-lane merger & low level protocol layer and CCI Master). CSI-2 receiver is connected to application engine through AHB bus. OVM methodology is used in the environment.
• Responsibilities:
• Developing the PHY interface model using OVM.
• Supported in developing top level environment in OVM.
• Developing test cases for hitting more coverage.
• Environment : Verilog HDL, System Verilog, OVM, C++
• Tools : VCS
• Verification of Ethernet controller

Jan 2011 – Jun 2011 · 5 mos

• The EMAC controller handles all functionality associated with moving packet data between memory and the 10/100/1000 Mbps Ethernet port. It implements major blocks like Transmit and Receive FIFO, DMA Controller for Transmit and Receive packet data transfers, Control and Status registers, 10/100 Mbps and 1Gbps MAC function. On the system bus side it provides AHB master interface for packet data transfers to/from memory and an AHB slave interface for configuring registers. At the PHY Interface, it can be configured to select MII, GMII, RMII or SMII interface.
• Responsibilities:
• Developing test plan for various filtering types, RX parser and queue manager blocks.
• Running the tests and debugging.
• Environment : Verilog HDL, e
• Tools : ncsim
• SOC Verification and gate level simulations for AMD Trinity fusion

Jan 2008 – Dec 2010 · 2 yrs 11 mos

• Llano is the first fusion project done in AMD. It is a fusion processor meant for Desktops with Core, Client Northbridge and Graphics card in a single package which is successfully taped-out in 32nm technology. Orochi is a fusion processor meant for Servers with Core and Unified Northbridge(Client Northbridge+Server Northbridge) in a single package. It is successfully taped-out in 32nm technology. Trinity Fusion is an extension to Llano fusion which additionally includes Client Southbridge. It is a fusion processor meant for Desktops with Core, Client Northbridge, Graphics card and Client Southbridge in a single package.Used OVM methodology in all environments.
• Responsibilities:
• Porting test cases at assembly level specific to the new features
• Running regressions and debugging at SOC level
• SOC Gate-level simulations and debugging
• Environment : C++, Verilog HDL, System Verilog
• Tools : VCS

Jul 2007 – Dec 2007 · 5 mos

• The PrimeCell GPIO is an AMBA slave module that connects to the Advanced Peripheral Bus (APB). The primeCell GPIO provides eight programmable inputs or outputs that you can control in two modes:
• Software mode through an APB bus interface
• Hardware mode through a hardware control interface
• GPIO System C Model verification done at different TLM abstraction Levels like untimed, timed and cycle-accurate.
• Responsibilities:
• Developed test plan, test case coding for GPIO in System C at different TLM Levels
• Developed monitors and scoreboards
• Regressions and debugging; SystemC
• Tools : Coware TLM Libraries, NC-sim