Ashish Chauhan

Product Manager

Delhi, India9 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Physical Design and Verification for advanced semiconductor technologies.
  • Proficient in multiple programming languages including Perl, Tcl, and Verilog.
  • Strong educational background with a Bachelor's in Electronics and Communication.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Verification.

Contact

LinkedIn

Skills

Other Skills

Static Timing AnalysisPhysical DesignC++LinuxCLogic DesignSynopsys PrimetimeSynopsys IC CompilerPhysical Verificationicc2Logic SynthesisPrime timeICC

About

Experienced Physical design & Verification Engineer with a demonstrated history of working in the semiconductors industry on 10 nm and 14 nm technology . Skilled in PNR, Timing Closure, Perl, Tcl, and Verilog. Strong engineering professional with a Bachelor's degree focused in Electronics And Communication from Chitkara University.

Experience

9 yrs 4 mos
Total Experience
2 yrs 4 mos
Average Tenure
6 yrs 11 mos
Current Experience

Cadence

4 roles

Principal Solutions Engineer

Jun 2025 – Present · 11 mos

Principal product validation engineer

Promoted

Jun 2024 – Present · 1 yr 11 mos

Lead Product validation Engineer

Promoted

Jun 2022 – Jun 2024 · 2 yrs

Product Validation Engineer II

Jun 2019 – Jun 2022 · 3 yrs

Intel corporation

Physical Design Engineer

Feb 2018 – May 2019 · 1 yr 3 mos · Bangalore

Rv-vlsi vlsi and embedded systems design center

Trainee - Physical design

Jul 2017 – Jan 2018 · 6 mos · Bengaluru, Karnataka, India

Secure meters limited

Intern

Oct 2016 – Jun 2017 · 8 mos · Himachal Pradesh, India

  • Nine month of industry experience .

Education

Chitkara University

Bachelor's degree — Electronics And Communication

Jan 2013 – Jan 2017

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