Mar 2013 – Sep 2015 · 2 yrs 6 mos · Greater San Diego Area

• SoC Functional Verification
• Exposure to SoC Architecture
• Bus Protocols (AMBA AHB,AMBA 3 AXI and ACE-AXI Bus protocols)
• Sub-system integration verification.
• UVM (in SystemVerilog) based Constrained Random Test Development.
• Native SoC Level Test Development in C.

Sep 2012 – Dec 2012 · 3 mos · Greater New York City Area

• Course - Computer Hardware Design
• Responsibilities:
• Prepare reference RTL Designs for students.
• Help students with topics in Digital Hardware Design and Verification.
• Assist students with their projects and home-works.
• Grade Lab Assignments on Architecture, Design and SystemVerilog Test-bench development.

Aug 2012 – Sep 2012 · 1 mo · Greater New York City Area

• Lead orientation activities like campus tour for new incoming international students.
• Contributed in creating a skit to help students make a smooth shift to New York City.
• Helped organize International Student Orientation of more than 2,000 students at Columbia University.

May 2012 – Aug 2012 · 3 mos · San Jose, California

• Run regression tests for RTL Design and generate code coverage database.
• Understand Functional Verification process flow from Testplan to Coverage Analysis.
• Generated and simulated a UVM based System Verilog testbench for an IP.
• Created Perl based Functional Verification project dashboard using HTML.
• Perl was used to :
• XLS file parsing
• Coverage Report file parsing
• Graph(Coverage vs Time) creation
• HTML webpage code generation

May 2009 – Jul 2011 · 2 yrs 2 mos · Bengaluru Area, India

• My responsibilities at Geodesic included :
• Scripting in Shell, C, C++.
• Embedded Hardware Design.
• Evaluation of IC components.
• Schematic Design(Cadence OrCAD).
• PCB Layout Design(Cadence Allegro Layout Tool).
• PCB testing and debugging prototypes using lab tools(Solder Station, DSO, Multimeter, Smart Tweezer, et. al.).
• BoM preparation and component ordering