R

Rahul E

Software Engineer

Bengaluru, Karnataka, India5 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 4+ years of experience in Synthesis and STA.
  • Expertise in Physical Aware Synthesis across technology nodes.
  • Published research in IEEE iSES on VLSI Design.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Timing Analysis.

Contact

LinkedIn

Skills

Core Skills

Physical Aware SynthesisStatic Timing Analysis (sta)

Other Skills

Clock Tree Synthesis (CTS)Place and Route (PNR)Timing AnalysisSI AnalysisIR Drop AnalysisTiming constraintsFormal Verificationphysical power-aware synthesisDesign Rule ChecksIR DROPElectromigrationClock Tree SynthesisRC ExtractionFloorplanningUPF

About

I am Rahul E, As a Synthesis/STA Engineer with a total of 4+ years of experience, I currently work at Qualcomm India and have previously worked at MediaTek. Master of Technology in VLSI Design from NIT Goa, with expertise in Physical Aware Synthesis/STA across various technology nodes (3nm to 28nm). Published a short paper on M.Tech project in IEEE iSES, and skilled in Physical Aware Synthesis, STA, CLP, LEC, QC checks, and various aspects of physical design including floor planning, place and route, timing analysis, SI analysis, and IR drop analysis.

Experience

5 yrs 1 mo
Total Experience
2 yrs 6 mos
Average Tenure
3 yrs 11 mos
Current Experience

Qualcomm

Synthesis/STA Engineer

Jun 2022 – Present · 3 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Physical Aware SynthesisStatic Timing Analysis (STA)Clock Tree Synthesis (CTS)Place and Route (PNR)Timing AnalysisSI Analysis+1

Mediatek

Synthesis/STA Engineer

Mar 2021 – May 2022 · 1 yr 2 mos · Bengaluru, Karnataka, India · Hybrid

Education

National Institute of Technology, Goa

Master of Technology - MTech — VLSI

Jan 2017 – Jan 2019

University BDT College of Engineering, Davanagere

Bachelor of Engineering - BE — Electronics and communication engineering

Jun 2012 – Jun 2016

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