PAVAN RAJ — Software Engineer

Project Title: Physical Implementation of Block Level SOC Design. Project Deliverables: Block level implementation of floor planning, power planning, placement, CTS and routing. Project description: In this Block includes 32 macros, 43000 standard cells, five clocks (three propagated and two generated clock) working on a clock frequency of 400 MHz, Power Consumption of 300mw, Operating voltage of 1.8V,up to 6 metal layers. Tools Used Synopsys ICC Compiler, Synopsys Prime time CORE SKILLS • Understood the CMOS Theory, digital design concepts, DSM technology, IC Fabrication Process. • Expert Knowledge of ASIC Flow (RTL to GDSII) and the stages involved in Physical Design Flow. • Working Knowledge of Linux, and TCL. • Proficient in Timing Analysis of STA for Register and Latch based designs with different Constraints such as Skew, Uncertainty. • Knowledge on I/O & OCV, CRPR, MCMM, SI and Low power design techniques. • Strong hands-on experience with Place-and-Route, Power Planning, IR Drop Analysis, CTS and Physical Verification. • Proficient in handling Floor Planning, and Static Timing Analysis, Sign-off closure congestion removal. • Understanding of Reliability issues like EM, Cross-talk, and Antenna effect. • DRC and LVS clean, fixing gate oxide integrity (antenna) violation. • The goal that is achieved ,timing under control in our design. • Have exposure to industry standard tools: IC Complier (APR), STA tools (like ICC, Primetime), STA tools (like ICC, Prime Time), IC Studio (Layout and Schematic editor), Hercules & Calibre ( DRC, LVS,PEX).

Stackforce AI infers this person is a VLSI design engineer with expertise in ASIC physical design and implementation.

Location: Bengaluru, Karnataka, India

Experience: 9 yrs 1 mo