AMISHA SANKHWAR — Product Manager
• STA & Synthesis Engineer with experience in advanced-node SoC designs (6nm/7nm) and block-level timing closure. • Hands-on in logic synthesis and physical aware synthesis, along with pre-layout and post-layout STA using Synopsys Design Compiler & PrimeTime. • Strong exposure to sign-off timing analysis, constraint validation, and multi-mode multi-corner timing checks. • Experience working on high-speed interface and multimedia blocks, contributing to timing optimization and ECO cycles. • Proficient in SDC debugging, LEC & CLP checks, and timing closure using DMSA and manual optimization techniques. • Skilled in Tcl scripting and constraint-quality checks to automate STA flows and improve timing predictability.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC development and verification.
Location: Hyderabad, Telangana, India
Experience: 3 yrs 8 mos
Skills
- Static Timing Analysis
- Synthesis
- Design Verification Testing
Career Highlights
- Expertise in advanced-node SoC designs.
- Proficient in static timing analysis and synthesis.
- Strong background in high-speed interface optimization.
Work Experience
AMD
Synthesis & STA Engineer (3 yrs 8 mos)
Qualcomm
Interim Engineering Intern (11 mos)
Education
Master of Technology - MTech at Malaviya National Institute of Technology Jaipur
Bachelor of Technology - BTech at Dr. A.P.J. Abdul Kalam Technical University
