Naveena Shirawal — Software Engineer

Experienced ASIC Physical Design Implementation Engineer with a strong track record in delivering high-performance, low-power SoCs across advanced technology nodes (3nm, 5nm, 7nm, 22nm). Personally accountable for full-chip and block-level implementation from RTL to GDSII, with hands-on expertise in synthesis, floorplanning, power/ground grid design, placement, CTS, routing, and physical signoff. Proven ability to drive timing closure, resolve signal/power integrity challenges, and ensure clean tapeouts through DRC/LVS/Antenna, EM/IR, and DFM signoffs. Currently engaged in next-generation flow and methodology development, collaborating closely with RTL and analog teams for silicon success. Passionate about solving complex low-power and high-speed design challenges with a sharp eye for quality and performance. To be involved cutting edge ASIC Physical Design where I can use my experience, educational background, and ability to work well with people and prove myself as a competent, contributing, and valuable asset for the organization. Core Competencies Strong understanding of the complete ASIC flow (Netlist to GDSII), with fluency in interfacing between stages and handling various I/O file formats. Expertise in Physical Design concepts: Floorplanning, Power planning, Timing-driven Placement, Clock Tree Synthesis, and Routing using Synopsys Reference Methodology. Solid STA skills: MCMM, OCV/AOCV, CRPR, inter-clock analysis, skew optimization, and time-borrowing. Extensive hands-on experience analyzing QoR reports across PnR stages; resolving setup/hold/DRC violations for timing closure. Developed custom TCL scripts for report parsing and timing data analysis, improving productivity and debugging efficiency. Strong debugging skills through log file analysis and optimization at various implementation stages. Thorough foundation in CMOS, Digital VLSI, Network Analysis, and Logic Design. Exposure to low-power architecture design and implementation strategies. 1 Indian Patents (Filed), 1 IEEE Publications Tools: *Design Compiler (Synopsys) *Fusion Comoiler (Synopsys) *ICC2 (Synopsys) *Innovus (Cadence) *Primetime (Synopsys) *Formality (Synopsys) *Calibre (Siemens) *Open Cv * Vivado (Xilinx) Instagram: shirawal_naveen X (Twitter): @naveenshirwal →Top skills Static Timing Analysis PNR RTL Open CV

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in ASIC Physical Design.

Location: Bengaluru, Karnataka, India

Experience: 11 yrs

Skills

Asic Physical Design
Static Timing Analysis

Career Highlights

Expert in ASIC Physical Design across advanced technology nodes.
Proven track record in timing closure and signal integrity.
Hands-on experience with industry-leading design tools.

Work Experience

Microsoft

ASIC Physical Design Engineer (Contract) (6 mos)

Intel Corporation

SOC Physical Design Engineer (Contract) (7 mos)

Physical Design Engineer (Contract) (2 yrs 4 mos)

Accenture

ASIC Physical Design Engineer (Silicon Engineering Analyst) (1 yr 11 mos)

RV-Academic Research Institution

Physical design Engineer intern (1 yr 3 mos)

Ultis Technologies Bangalore

Design Engineer (client BEL) (2 yrs 3 mos)

B.V.Bhoomaraddi College of Engneering and Technology

Ass.Professor (3 yrs 11 mos)

Indian Air Force

Prepared For IAF (10 mos)

nanoPix ISS (P) Ltd. Hubli Karnataka

RTL Design Engineer Intern (7 mos)

Education

Foundation degree at Synopsys

Post Graduate Diploma at RV College Of Engineering

M.Tech at B V B College of Engg. & Technology, HUBLI

Bachelor of Engineering - BE at BLDEAs College of Engg. & Technology, BIJAPUR

Diploma Education at NSE India

Naveena Shirawal

Software Engineer

Bengaluru, Karnataka, India11 yrs experience

Key Highlights

Expert in ASIC Physical Design across advanced technology nodes.
Proven track record in timing closure and signal integrity.
Hands-on experience with industry-leading design tools.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in ASIC Physical Design.

Contact

Skills

Core Skills

Asic Physical DesignStatic Timing Analysis

Other Skills

Floor PlanningPlacementRoutingPrime Time by SynopsysSign offCross TalkStatic Timing Analysis STALayout Versus Schematic (LVS)Block Level Design ImplementationTCLPrime TimeFusion compilerPhysical DesignIR DropIntel lynx flow

About

Experience

11 yrs

Total Experience

2 yrs 5 mos

Average Tenure

6 mos

Current Experience

Microsoft

ASIC Physical Design Engineer (Contract)

Nov 2025 – Present · 6 mos · Bengaluru, Karnataka, India · On-site

Intel corporation

2 roles

SOC Physical Design Engineer (Contract)

Jun 2024 – Jan 2025 · 7 mos · Bengaluru, Karnataka, India

Physical Design Engineer (Contract)

Jul 2021 – Nov 2023 · 2 yrs 4 mos · Sunnyvale, California, United States · Remote

Intel NEX Cloud Networking Group (NCNG) delivers best-in-class Ethernet products and is part of the Connectivity Group which is at the heart of Intel's transformation from a PC company to a company that powers the cloud and billions of smart, connected computing-devices. EPG's compelling Ethernet products move the world's data and are the foundations of cloud service and telecommunications data centers. We are a team of problem solvers, experimenters, and innovators who are dedicated to designing the network technologies that currently lead and continue to transform datacenter ecosystems. As a world-class organization, And it's based on 3nm technology node, handling 2 blocks with 2M instance, Intel cheetah flow setup, Fusion compiler/innovas, genus, and familiar with Intel flows
Roles Responsibility and Challenges
PnR – Floor Planning, Placement, CTS, and Routing using Fusion Compiler and Innovus with Cheetah Intel flow
FloorPlan with multiple dimension Challenges
Floorplan was a major challenge, in terms of Utilization, Timing, and congestion.
Multiple Floorplan iterations to meet requirements for top-level design, between Utilization, Congestion, and Timing issues with both the tools FC/Innovus to get the best result.
Responsible for delivering one Functional Unit Block Implementation
PnR – Floor Planning, Placement, port analysis, Timing Analysis, Timing closure
Analyzing and reporting port connections, to find port-to-cell distances and fixing overlaps

Floor PlanningPlacementRoutingPrime Time by SynopsysSign offCross Talk+24

Accenture

ASIC Physical Design Engineer (Silicon Engineering Analyst)

Jun 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

ASIC Physical Design Engineer

Rv-academic research institution

Physical design Engineer intern

Mar 2020 – Jun 2021 · 1 yr 3 mos · Bengaluru, Karnataka, India

Working as an Physical Design Engineer intern with the technology node 22nm 45nm projects, handled two blocks from RTL to GDSII with complete eco fixing
Multiple iterations of the design block to ensure congestion-free by modifying floor plan, updating routing and placement blockages based on analysis from GR for congestion map Legalized placement (Timing Driven) with P/G nets pre-routed, HFN synthesized, SCAN chain reordered, congestion and timing under control design is performed for CTS(Classic flow) to meet logical DRC and clock tree targets (skew and insertion delay)

Floor PlanningPlacementRoutingPrime Time by SynopsysSign offCross Talk+22

ultis technologies bangalore

Design Engineer (client BEL)

Jun 2017 – Sep 2019 · 2 yrs 3 mos · Bengaluru, Karnataka, India

2 years experience in RTL design and validation on FPGA boards.
Key areas of work include FPGA configuration schemes, DDR3 controller interfaces, PCIe, High-Speed Interface, and I2C interfaces.
Project Title: ARINC 717 Simulators, Tools: Xilinx ISE 14.4 , Language: Verilog
Project Description:
This project is used to implement ARINC 717 Simulator. In this simulator the parallel data is received from PCI bus and converted in to serial Bi-phase M type data, and it is transmitted to ARINC 717 card or it may be made loopback for loop back test. The received data which may be loopback data or ARINC 717 data, which is Bi phase M it is converted in to Binary format and then to make Frames. And these Frames are sent through PCI bus to the processor.
Contribution:
Conversion of Bi-phase M type data in to binary form and vice-versa.
And to implement ARINC 717 Protocol
And interfacing with PCI bus to receive and send parallel data
Project Title: CCDL (Cross Channel Data Link)
Tool: Altera-Quartus 13.0
Project Description:
This project is used to implement CCDL protocol, which is used to make interface with CCDL Simulator and ATE (Automated Test Equipment). Interface between CCDL simulator and FPGA is serial and Interface between FPGA and ATE is parallel. FPGA will receive serial Bi-phase L type data and address from CCDL Simulator, which is stored in to give address location.
Contribution:
Conversion of Serial Bi-phase L type data in to binary form and Vice-Versa.
Implementation of Clock recovery form Bi-phase L data.
Implementation of Loop back Test.
And interfacing with PCI bus to receive and send parallel data.
Project Title: PCM to Ethernet Converter
Tools: Lattice semiconductor 7.2
Language: VHDL
Project Description:
The PCM (Pulse code modulation) data which is Manchester type, which generated from the simulator. The received serial Manchester data is converted in to binary form.