Raja Mouli Y. — Software Engineer
I’m a Physical Design Engineer with over 6 years of experience delivering RTL-to-GDSII implementations across advanced process nodes, including 3nm, 7nm, 16nm, and 28nm. I’ve contributed to 3 successful tapeouts and currently drive high-frequency 3nm designs (up to 4M+ gates, 180+ macros) with stringent PPA and timing goals. My expertise spans floorplanning, placement, CTS, routing, STA, and signoff (DRC/LVS, IR/EM), using industry-standard EDA tools like Fusion Compiler, Innovus, ICC2, PrimeTime, and Calibre. I specialize in congestion handling, timing closure across 15+ PVT corners, and clock power optimization. I’m passionate about solving complex PD challenges, collaborating across design teams, and delivering signoff-ready layouts on aggressive schedules.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 8 mos
Skills
- Physical Design
- Timing Closure
Career Highlights
- Over 6 years of experience in Physical Design Engineering.
- Expertise in RTL-to-GDSII implementations across advanced process nodes.
- Contributed to 3 successful tapeouts in high-frequency designs.
Work Experience
Hewlett Packard Enterprise
ASIC Physical Design Engineer (4 mos)
Cisco
Physical Design Engineer (2 yrs 9 mos)
eInfochips (An Arrow Company)
ASIC Physical Design Engineer (2 yrs 10 mos)
Cerium Systems
Physical Design Engineer (1 yr 11 mos)
Intel Corporation
SoC Design Engineer (1 yr 11 mos)
Moslogi Technologies LLC
Physical Design Engineer (1 yr 7 mos)
Education
Master’s Degree at Sri Venkateswara College of Engineering and Technology
Bachelor of Technology - BTech at Madanapalli Institute of Technology & Science, Madanapalli
High School at APR School, Lepakshi
