May 2016 – Aug 2019 · 3 yrs 3 mos · Singapore

• Worked for Top level Integated Modem top mdsys Design, internally cosists of 2 subblocks
• Physical Designed Full Flat Chip consists of IO , Efuse PADs, 134 Macros and standard cell core logic
• (1) ASIC Physical Design : Floor Plan, Placement, Clock Tree Synthesis, Routing and Post Route Optimization.
• (2) Timing Analysis : Static Timing Analysis, Noise and Cross Talk analysis.
• (3) IR Drop Analysis : Static and Dynamic IR Drop,Resistivity Check.
• (4) Physical Verification : LVS, ERC, DRC, Softcheck, AntennaCheck,
• (5) Formal Verification

Aug 2014 – Aug 2016 · 2 yrs · Bengaluru, Karnataka, India

• Responsible for closing Venus and Vcodec designs (Floorplan to GDSII), need to close the Vcodec top in all timing corners, to guide and drive the team to close the internal Vens sub-hms to make sure we will meet the metrics on time.Implemented ICC2 for 14nm Vcodec block PnR design & tapeout first time in Bangalore design center. Vcodec top is closed with 79% std cell utilization at PRO stage. Converging the design with high number of Feed Through(FT) count

Jan 2012 – Jan 2014 · 2 yrs · Greater Paris Metropolitan Region

• Spreading of one digital logic module cells is a requirement. This works as light detector cells. But it was leading to routing congestion and also power consumption is more. Experimented with different spreading techniques like first module wise alone spreading and overall block. After some floor-planning and placement iterations and optimized the design for congestion and timing the results. Final results were found to be satisfactory in meeting the timing, power and other design constraints.

Jun 2010 – Dec 2012 · 2 yrs 6 mos · Greater Hyderabad Area

• The tasks handled are Floor plan, Place & Route, STA and bring the block to timing closure with SI, manual ECOs, and Clean DRC/LVS issues at block level. 1.8M of instance count, 72 macros and major run time block. The ecos are aggressive, implemented top level ecos and in parallel closed block level internal design.