Shivakumargowda P

Software Engineer

Bengaluru, Karnataka, India4 yrs 9 mos experience
Most Likely To Switch

Key Highlights

  • Expert in Physical Design and Timing Closure.
  • Proficient in multiple programming languages including Python and Verilog.
  • Strong background in Analog Circuit Design and ESD.
Stackforce AI infers this person is a Physical Design Engineer with expertise in VLSI and Analog Circuit Design.

Contact

LinkedIn

Skills

Core Skills

Physical DesignTiming ClosureStaScriptingAnalog Circuit Design

Other Skills

Clock Tree SynthesisPlace & RouteTCLTimingPhysical VerificationDesign Rule Checking (DRC)Layout Versus Schematic (LVS)TweakerRTL CodingVerilogCadence VirtuosoPython (Programming Language)Electrostatic Discharge (ESD)Python automationpytest

About

Currently working as a Senior Physical design Engineer in Qualcomm, Bangalore. Completed ME in VLSI Design from Manipal school of information sciences (2019-21), Manipal.

Experience

4 yrs 9 mos
Total Experience
1 yr 7 mos
Average Tenure
1 yr 11 mos
Current Experience

Qualcomm

Senior Physical Design Engineer

Jun 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

Clock Tree SynthesisPlace & RouteTiming ClosureTCLTimingScripting+9

Mediatek

Physical Design Engineer

Jun 2022 – May 2024 · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

  • Direct Contractor @Mediatek
STATCL

Kpit

Software Engineer

Jul 2021 – Jun 2022 · 11 mos · Pune

ScriptingPython (Programming Language)

Stmicroelectronics

Analog Design Engineer

Sep 2020 – Jul 2021 · 10 mos · Noida, Uttar Pradesh, India

Analog Circuit DesignElectrostatic Discharge (ESD)

Education

Manipal School of Information Sciences

Master's degree — VLSI

Jan 2019 – Jan 2021

Ramaiah Institute Of Technology

Bachelor's degree — Medical Electronics

Jan 2013 – Jan 2017

Stackforce found 100+ more professionals with Physical Design & Timing Closure

Explore similar profiles based on matching skills and experience

MD

Mario Da Costa

Engineering Manager

at Intel Corporation

Bengaluru, India25 yrs 10 mos exp
Rajesh Gottumukkala

Rajesh Gottumukkala

Senior Engineering Manager

at Google

Bengaluru, India19 yrs 4 mos exp
DFTStatic Timing Analysis
Animesh Pandey

Animesh Pandey

Staff Engineer

at Qualcomm

Noida, India10 yrs 9 mos exp
ASICStatic Timing Analysis
SC

Shwetha Chander

AE Architect - GCS

at Cadence Design Systems

Bengaluru, India20 yrs exp
EDAVLSI
Aarohi Agrawal

Aarohi Agrawal

Product Manager

at Google

Kerala, India9 yrs 10 mos exp
Market StrategyPhysical Design Engineering
Akshay Jain

Akshay Jain

Senior Staff Engineer

at Qualcomm

India6 yrs 11 mos exp
ASICIntegrated Circuit DesignVLSI
Venugopal Raavi

Venugopal Raavi

Silicon Design Engineer 2

at AMD

Hyderabad, India4 yrs 2 mos exp
Python (Programming Language)Logic Synthesis
Pratik Dave

Pratik Dave

Staff Engineer

at MediaTek

Bengaluru, India4 yrs 3 mos exp
Static Timing AnalysisLogic Synthesis