R

Rahul Thakur

CEO

Bengaluru, Karnataka, India16 yrs 9 mos experience

Key Highlights

  • 15 years of experience in Physical Design and STA
  • Led teams of up to 15 engineers in complex projects
  • Expertise in low power design and multi power domain implementation
Stackforce AI infers this person is a VLSI design expert with extensive experience in ASIC and SoC development.

Contact

LinkedIn

Skills

Core Skills

Physical DesignSta

Other Skills

Design Rule Checking (DRC)Place & RoutePhysical VerificationSystem on a Chip (SoC)UPFASIC DesignStatic Timing AnalysisPrimetimeDesign for ManufacturingDesign OptimizationClock Tree SynthesisClock DistributionScriptingDesign FlowFloor Plans

About

15 Years of Total Experience of STA/Physical Design Physical Design/Implementation Engineer (ASIC/SoC) ================================== Hands-on experience with:( Top and Block Level) Floor planning & Power Planning Low power design Clock Tree Synthesis Timing Optimization STA Power distribution, pin placement . Physical design verification. Good software and scripting skills - tcl => Experience of tape out in various techno Node ; 90nm,65nm,40nm,32nm,28FDSOI,10nm,7nm,4nm => worked as Techlead for few Projects and guided team of 4 to 15 PD engineers =>  Hands-on experience in top level PD tasks - Floorplanning, Power Structure planning, Placement, Clock Tree Synthesis, Routing and Signoff cheks : STA, Physical Verification , EMIR Fixes  Hands-on experience in Low Power Implementation and Multi Power domain design implementation , drawing upon UPF flow knowledge  Basic Knowledge of DFT.  Understanding of Timing constraints and SPEF Extraction Issues.  Know-how related to foundation IPs like memories , Analog blocks and their integration guidelines.  Analyze timing within PD environment and using STA tool, to achieve timing closure by generating and applying ECO  Expertise with ASIC design flows, procedures. Ability to contribute in Physical Design methodology and automation.  Experience of mentoring small team for Back-End Implementation (From Netlist to TO )  Flexible to work in a cross functional and multi-site team environment, spanning different time zones ACADEMIC DETAILS

Experience

16 yrs 9 mos
Total Experience
3 yrs 3 mos
Average Tenure
1 yr 11 mos
Current Experience

Samsung semiconductor

Technical Lead

Jun 2024 – Present · 1 yr 11 mos · On-site

  • Synthesis STA and PD

Mediatek ( as client)

Senior Physical Design Engineer

Jun 2023 – Feb 2026 · 2 yrs 8 mos · Bengaluru, Karnataka, India · On-site

  • Leading Team of 10-15 physical design engineer to drive all PD activities starting from Netlist to GDS with closure of all Signoff check
Design Rule Checking (DRC)Place & RoutePhysical VerificationSystem on a Chip (SoC)UPFASIC Design+16

Intel corporation

Senior Physical Design Engineer

Feb 2022 – Mar 2023 · 1 yr 1 mo · Bengaluru, Karnataka, India

  • Job Responsibilities:
  • => implementation of block level design from RTL to GDS
  • => Responsible for Timing closure, physical verification
  • => Part of full chip level STA closure
  • => working closely with CAD Flow team and IP owners, during various stage of implementation
Shell ScriptingPNRPlace & RouteSystem on a Chip (SoC)UPFASIC Design+15

Stmicroelectronics

4 roles

Staff Engineer

Jul 2020 – Feb 2022 · 1 yr 7 mos

  • Job Responsibilities:
  • => Responsible for Top level Integration ( implementation of Top level design from Netlist to GDS)
  • => Responsible for Timing closure, physical verification (full chil level)
  • => Leading team of 4-6 Backend Designer
  • => working closely with CAD Flow team and IP owners, during various stage of implementation
Design Rule Checking (DRC)Shell ScriptingPNRPlace & RouteUPFPrimetime+20

Tech Lead

Promoted

Jul 2015 – Jun 2020 · 4 yrs 11 mos

  • => Responsible for Top level Integration ( From Netlist to GDS), Timing Closure, EM/IR Fix , PV closer
  • .Responsible for Complete Implementation of Blocks and SoC from Netlist to GDS .
  • .Done SoC level Physical Verification.
Design Rule Checking (DRC)Shell ScriptingPNRPlace & RouteUPFPrimetime+18

Sr.Design Engineer

Apr 2012 – Jun 2015 · 3 yrs 2 mos

  • Job Profile :
  • . Responsible for IO Ring development( using Innovus)
  • . Responsible for PnR at Block level.
  • . Devlopment and verification of EDA Views for various IPs.
Design Rule Checking (DRC)Shell ScriptingPNRUPFPrimetimeDesign for Manufacturing+15

Design Engineer

Feb 2010 – Mar 2012 · 2 yrs 1 mo

  • Job Profile :
  • Generation and Verification of EDA Views for wide variety of Analog and Digital IPs ( Including PLL , IOs , Voltage Sensor, HDMI)
  • Characterization of the I/O library.
  • Responsible for Debug and solution of Various Problem at CAD Flow level for Various Technology
  • Physical Verification .
  • Perform Various Validation check and debug Error
Design Rule Checking (DRC)Shell ScriptingPNRUPFParasitic ExtractionVery-Large-Scale Integration (VLSI)+8

Kalol institute of technology

Lecturer

Jul 2009 – Dec 2009 · 5 mos

  • Senior Lecturer at KIT

Stmicroelectronics

2 roles

INTERN

Sep 2008 – Apr 2009 · 7 mos

  • Tool Developer, Design Engineer,Design Auto mater

Trainee Engineer

Sep 2008 – Apr 2009 · 7 mos

  • Job Profile : Tool Design
  • · I have developed Wrapper for Data Base Using Scripting in
  • TCL. Also many script related to Automation has been
  • Prepared using TCL/TK.
  • Design of Block for I/O cell
  • · I have Design some Block for I/O cell according to
  • Specification of I2C Bus for 100 Kbps which contains
  • design of Schmitt trigger, Level Shifter etc .
  • PROJECT
  • 1. Design and Characterization of I/O cells Compatible to I2C Bus :
  • [Organization: ST Microelectronics, Greater Noida]
  • The aim of this Project is to design various block of I/O cell for I2C bus like Schmitt trigger,
  • Level Shifter [Using Virtuoso] and characterize that design over various PVTSC
  • condition.
  • Tools Used: Eldo, Virtuoso
  • 2. Implementation of Checker Board Algorithm for Memory Testing:
  • [Organization: Nirma Institute of Technology, A'bad]
  • Tools Used: Xilinx ,Modelsim Language : VHDL

Education

NIRMA INSTITUTE OF TECHNOLOGY

M.Tech — VLSI

Jan 2007 – Jan 2009

South Gujarat University

B.E. — EC

Jan 2001 – Jan 2005

C.K.Pithawala

B.E. — EC

Jan 2001 – Jan 2005

Aroma school

gujarati

Jan 1987 – Jan 1999

Aroma high

G.S.E.B

Aroma school

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