Vijeth Anchatgeri

Software Engineer

India11 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Strong expertise in Digital Design and Verification.
Proficient in Static Timing Analysis and Debugging.
Hands-on experience with leading EDA tools.

Stackforce AI infers this person is a Semiconductor Design Engineer with strong capabilities in Digital Design and Verification.

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Skills

Core Skills

Digital DesignFunctional VerificationStatic Timing AnalysisDebuggingDc-topo SynthesisTiming CorrelationVerilog

Other Skills

System VerilogTCLMulti voltage library setupECO timingFormal Equivalence Verificationsynopsys formalityequivalence checkingsynopsys prestoCvhdl 2008Cadence VirtuosoModelSimCadence SpectreXilinx ISEChipscope

About

Highly motivated, self driven individual with a strong desire to pursue career in semiconductor industry, currently pursuing Masters in VLSI Design from R.V College of Engineering,Bangalore. My Skill sets include Strong Digital design. Good coding skills in Verilog HDL Knowledge of Static Timing Analysis(STA), ASIC Design Flow. Fair knowledge on Xilinx design tools (IP Core, Chipscope, ISE). Architecture’s ARM Cortex M3 and 8051. Knowledge on HDL Cosimulation and Simulink Models. EDA Tools Cadence Virtuoso ADE, Synopsys Design Compiler Synopsys Formality Synopsys VCS Cadence NC, Cadence Spectre, Mentor Graphics QuestaSim 6.4c and ModelSim6.3f Xilinx 10.1, ISE, Hardware Description Languages [HDL's] HDL Verilog - [IEEE Std 1364-2005] VHDL - [IEEE Std 1076-2008] System Verilog for Design - [IEEE Std 1800-2012] Scripting for Automation TCL

Experience

11 yrs 3 mos

Total Experience

3 yrs 9 mos

Average Tenure

7 yrs 8 mos

Current Experience

Intel corporation

Design Engineer

Sep 2018 – Present · 7 yrs 8 mos · Bengaluru, Karnataka, India

VerilogSystem VerilogDigital designFunctional verification

Mediatek

2 roles

Senior Engineer, SoC Integration

Promoted

Jun 2018 – Sep 2018 · 3 mos · Bengaluru, Karnataka, India

Setting up Flat SoC STA environment and Multi volatge library setup for Various DVFS
Conditions.
Analyze the STA log Files, Summarize Log Errors, Verify correctness of Libs, netlist/spef
versions, POCV derates.
Debugging linking issues, black boxes and SDC constraint issue Causing PTE and UITE
Errors.
Analyze Timing reports of critical PVT RC corners and DVFS conditions for Func Mode.
Perform Timing correlation b/w Flatten SoC and Block level, and feedback SoC and Block
level Timing Mis-correlation to block owners.
Responsible for Point-to point timing checks at partition interfaces.
Responsible for debugging the longer SDC read time and Feedback SDC owner about quality
of SDC.
Developed TCL procs/scripts to debug STA constraint issues and Timing correlation.
Worked closely with DFT and DV-Simulation team for delivery of HACK SDF, for IR Drop and GLS during early TECO cycles.
Responsible for debugging of un-annotated delays, Netlist-SDF Mismatch issues.

Static Timing AnalysisTCLDebuggingMulti voltage library setup

Engineer, SoC Integration

Jan 2016 – May 2018 · 2 yrs 4 mos · Bengaluru, Karnataka, India

Responsible for Block level DC-Topo synthesis of block involving Memory controller and DDRPHY. Creating the scenarios for DVFS Conditions, Identify critical scenario for first compile.
Preparing DC-Topo synthesis recipes with various flavor of libs and optimization switches.
Analyze critical paths in different MCMM Scenarios, Identifying Synthesis constraint issues, worked closely with PD for DEF issues.
LEC b/w RTL and Netlist.
Setting Pre-STA at Block level, Performing DC and PT Timing correlation, Perform Fix ECO timing and roll back ECO's in DC.
Performing Internal QC Checks, Netlist quality check and SDC quality using conformal constraint debugger.
Responsible for Block sign-off, with QC checks and Hand-off Netlist to Backend team

DC-Topo synthesisTiming correlationECO timing

Synopsys

Intern, R&D,Design Group

Jan 2015 – Jan 2016 · 1 yr · Bengaluru, Karnataka, India

Develop effective RTL Test cases using Verilog and System Verilog to achieve Verification
goals
Creating Test cases on synthesizable constructs of System Verilog, to support for design
Synthesizing using DC, Extracting gate level netlist and do equivalence check
Performing Formal Equivalence Verification at RTL-RTL, RTL-Netlist, RTL-DDC
Creating the Regression Test Suite, Regression Setup, Preparing Regressions.
Running the Regressions, Analyzing the Regression Results
Debugging Failing Verifications, Analyzing the Log files
Test Cases to achieve Code-Coverage goals
Develop the TCL Scripts, to automate the verification process
Expertise in Synopsys Front End Tools, Synopsys VCS, Design Compiler [DC], Formality
Knowledge on writing Verilog Testbenches for functional Verification
Gained a strong understanding of Verilog [IEEE 1364-2005] and SystemVerilog [1800-2012]
Design constructs.
Gained strong coding Skills in Verilog, Design constructs of System Verilog, and deep
understanding of Digital design.