Rishabh Bhargav — Product Engineer
• Design verification (SoC DV, IP DV): Expertise in creation of verification plan, test bench development, generation of constrained random stimuli, feature verification and debug, functional and code coverage analysis/closure. • Formal Verification: Expertise in doing SoC checks/IP verification using formal techniques • Programming Languages: C/HDL (Verilog) • Scripting languages: Perl, TCL • Tools: NCSIM, IEV, JG (FPV, CSR) , vManager, vPlanner
Stackforce AI infers this person is a Design Verification Engineer specializing in semiconductor and hardware verification.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 10 mos
Skills
- Formal Verification
- Universal Verification Methodology (uvm)
- System On A Chip (soc)
- Object-oriented Programming (oop)
Career Highlights
- Expert in design verification for SoC and IP designs.
- Proficient in formal verification techniques.
- Strong programming skills in C/HDL and scripting languages.
Work Experience
Design Verification Engineer (5 yrs 1 mo)
Texas Instruments
Design Verification Engineer (2 yrs 9 mos)
NVIDIA
Memory Subsystem Verification Intern (5 mos)
