Chaitanya Kancherla — Engineering Manager

Have 15+ years of experience in Design Verification. Worked on IP verification of different protocols (PCIE/USB3/USB4/Display) PHY's and architectures. Good knowledge on Low power mixed signal verification and GLS, Worked on different Methodologies like VMM, OVM and UVM. Worked on Ethernet, Fiber Channel, Video/Audio protocols. Developed VIPs from scratch for proprietary protocols. Developed test benches using Verilog, System Verilog with UVM, C and C++. Have good understanding of OOPS concepts and constrained random verification environments. Worked on SS and IP level verification of AMBA NOCs. As a Verification Lead, I truly believe beyond a point verification is "architecture forensics".

Stackforce AI infers this person is a Design Verification Lead in the semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 18 yrs 2 mos