Subhash Chandra Roy

Software Engineer

Bengaluru, Karnataka, India20 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Static Timing Analysis and ASIC Design.
  • Proven track record in Formal Verification and Synthesis.
  • Strong background in VLSI and FPGA development.
Stackforce AI infers this person is a VLSI and ASIC design expert with extensive experience in formal verification and timing analysis.

Contact

LinkedIn

Skills

Core Skills

Static Timing AnalysisAsic DesignSynthesisVlsiTiming ClosureFormal VerificationAsic Verification

Other Skills

ASICLogic SynthesisDebuggingSystemVerilogC++STARTL integrationDesign Engineeringpre-layout timing analysisretimingCDCMTBFPhysical SynthesisPower EstimationCPF

About

I am a go-getter with optimistic approach towards life. Specialties: Synthesis, Formal Verification, STA. My objective is to achieve optimum result and meet schedules by the virtue of technical know-how & expertise, analytical skills, innovative ideas and to grow with the organization in a challenging work environment. PS: Please don't contact me for AMWAY related stuff. I am NOT interested for it.

Experience

20 yrs 6 mos
Total Experience
3 yrs 5 mos
Average Tenure
10 yrs 6 mos
Current Experience

Broadcom inc.

2 roles

Principal Engineer

Promoted

Oct 2019 – Present · 6 yrs 7 mos

Static Timing AnalysisTiming ClosureASICVLSILogic SynthesisDebugging+4

Staff Engineer

Nov 2015 – Nov 2019 · 4 yrs

  • Working on STA, Synthesis, FV, Spyglass & RTL integration.
STASynthesisFormal VerificationRTL integrationStatic Timing Analysis

Lsi corporation

ASIC DvDs Engineer Senior

May 2013 – Nov 2015 · 2 yrs 6 mos · Bangalore

  • Working as Senior Development & Design Engineer.
ASICVLSIDesign EngineeringASIC Design

Nvidia

2 roles

Sr. ASIC Engineer

Mar 2013 – May 2013 · 2 mos

ASIC Engineer

Aug 2011 – Mar 2013 · 1 yr 7 mos

  • Working on pre-layout timing analysis and timing closure. Also taking care of retiming, CDC & MTBF, full chip trans, cap & noise/glitch fixes.
pre-layout timing analysistiming closureretimingCDCMTBFStatic Timing Analysis+1

Open silicon

ASIC Design Engineer

Jun 2009 – Aug 2011 · 2 yrs 2 mos

  • Worked on Synthesis, Physical Synthesis, Formal Verification, Power Estimation, CPF and STA..
SynthesisPhysical SynthesisFormal VerificationPower EstimationCPFSTA

Da-iict

Teaching Assistant

Aug 2007 – Apr 2009 · 1 yr 8 mos · Gandhinagar

  • I used to assist Professor's in tutorials & course work and also used to conduct VLSI labs & practicals for under-graduate students.
  • Worked extensively on FPGAs and custom design tools like Magic & LT-Spice.
VLSIFPGAscustom design tools

Einfochips

2 roles

ASIC engineer

Jun 2006 – Jul 2007 · 1 yr 1 mo

  • During this period I had worked mainly on ASIC Verification.. I had worked on AMBA AHB, AHB2APB Bridge, USB2.0 etc.. I was involved in verification of 3 complex SOCs..
  • I had contributed in development of AMBA AHB SV-VIP & also made it AVM compliant..
  • I had worked on implementation of assertions, checkers, functional & Code coverage etc..
ASIC VerificationAMBA AHBUSB2.0

Graduate Engineering Trainee

Jan 2005 – Jan 2006 · 1 yr · Ahmedabad Area, India

  • Learning SV, Understanding different testing architectures, Creating test benches, Writing assertions, Verified fifo and ethernet
SVtest benchesassertions

Education

Dhirubhai Ambani Institute of Communication & Information Technology

M.Tech — VLSI

Jan 2007 – Jan 2009

Dharmsinh Desai University

Bachelor of Engineering — Electronics & communication

Jan 2002 – Jan 2006

Kendriya Vidyalaya

Jan 1990 – Jan 2002

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