James George — Software Engineer
Experienced Design Verification Engineer with a demonstrated history of working in the VLSI Industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, SVA, Functional and code coverage, Verilog, GLS, Bus Certification, Power Aware simulations, Perl Scripting and Debugging skill and Protocols like Ethernet (100G/50G/25G/10G/5G/2.5G/1G/100M/10M - MII, RMII, RGMII, SGMII, USXGMII, XSBI), PCIe (Gen1/Gen2/Gen3/Gen4), Functional Safety(FuSA), TestChips etc.
Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in verification methodologies and protocols.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 6 mos
Skills
- Design Verification
Career Highlights
- Expert in VLSI design verification methodologies.
- Proficient in UVM and SystemVerilog for complex projects.
- Strong background in functional safety and protocol verification.
Work Experience
Qualcomm
Senior Lead Engineer (2 yrs 4 mos)
Senior Design Verification Engineer (2 yrs 11 mos)
Samsung Electronics
Senior Design Verification Engineer (1 yr)
SmartPlay Technologies - An Aricent Company
Design Verification Engineer (2 yrs 9 mos)
Truechip Solutions
Design Engineer (1 yr 1 mo)
Maven Silicon
Project Intern (5 mos)
Education
Master of Technology - MTech at Birla Institute of Technology and Science, Pilani
ADVANCED VLSI RN COURSE at MAVEN SILICON
B.Tech at TKM College of Engineering , Kollam
at Govt model sen sec school portblair
