Ashish Agrawal

Director of Engineering

Bengaluru, Karnataka, India9 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in UVM/SystemVerilog testbenches.
  • Proficient in directed and constrained random verification.
  • Strong background in functional verification.
Stackforce AI infers this person is a VLSI verification expert with a focus on functional testing and design engineering.

Contact

LinkedIn

Skills

Core Skills

Functional Verification

Other Skills

Sub-system verificationIP verificationCC++SystemVerilogVery-Large-Scale Integration (VLSI)Shell ScriptingSVUVMPCIE 4QVIP VIP PCIE4Python

About

• Functional Verification • Coding UVM/SystemVerilog based testbenches. • Experience in directed, constrained random verification Specialties: SV, UVM, PCIE 4, QVIP VIP PCIE4, Python, Shell Scripting

Experience

9 yrs 10 mos
Total Experience
2 yrs 5 mos
Average Tenure
--
Current Experience

Qualcomm

Senior Lead Engineer

Nov 2018 – Jul 2022 · 3 yrs 8 mos · Noida · On-site

  • Worked on Sub-system verification and IP verification.
Sub-system verificationIP verificationFunctional Verification

Amd

Senior Design Engineer

May 2018 – Nov 2018 · 6 mos · Bengaluru Area, India · On-site

Mentor graphics

Senior Member Of Technical Staff

Sep 2015 – May 2018 · 2 yrs 8 mos · Noida Area, India

Mirafra technologies

Design Verification Engineer

Aug 2011 – Aug 2014 · 3 yrs · Bangalore

Education

Indian Institute of Technology (Banaras Hindu University), Varanasi

Bachelor of Technology - BTech

Jan 2007 – Jan 2011

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