Avinash Sanadhya

Operations Associate

Bengaluru, Karnataka, India14 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 12 years of ASIC Verification experience
Expert in UVM/System Verilog testbench development
Proven track record in full-chip validation

Stackforce AI infers this person is a seasoned ASIC Verification Engineer with extensive experience in semiconductor design and validation.

Contact

Skills

Core Skills

Asic VerificationSoc VerificationFull-chip ValidationDebuggingAutomationScriptingTool DevelopmentDesign VerificationMethodology

Other Skills

VerilogSystemVerilogUVMAXI ProtocolTestlist DebuggingPerl ScriptingRTL DesignPerlDebug Tool DesignOVM/UVM MethodologyOpen Verification MethodologyLogic DesignLECLintraAMBA AHB

About

- 12 plus years of experience in the field of ASIC Verification. - Worked on SoC verification for multiples blocks for NXP semiconductor. - Worked on IP verification on multiple block for different client. - Hands on experience on testbench development using UVM/System Verilog for multiple block like Cache controller, debug block and some module of UFS. - Worked on integration of multiple blocks to top level verification environment. - Written multiple testcases/sequence, cover points in various projects. - Worked on verification of axi master driver BFM development using UVM and SV. - VISA debug tool design for debugging purpose for intel(client) using perl script. - Worked on lintra tool for linting purpose and Logical Equivalence check tool at intel. - Handled regression and debuging activities at cluster level of processors at intel. - Worked on full-chip validation/verification with intel team. - Worked on System verilog,Verilog,Vhdl,UVM,Perl and other scripting language. - Worked on I2C,AMBA-AXI protocols. - Have done mini projects like IC tester,traffic signal using verilog.

Experience

14 yrs

Total Experience

2 yrs

Average Tenure

3 yrs 9 mos

Current Experience

Stmicroelectronics

2 roles

Manager

Promoted

Oct 2024 – Present · 1 yr 7 mos · Noida, Uttar Pradesh, India

Staff Engineer

Aug 2022 – Oct 2024 · 2 yrs 2 mos · Noida, Uttar Pradesh, India

Amd

Member of Technical Staff

Nov 2021 – Aug 2022 · 9 mos · Bengaluru, Karnataka, India · Remote

Smartplay technologies - an aricent company

Senior Engineer at Aricent Technologies Holdings LTD

Dec 2016 – Apr 2022 · 5 yrs 4 mos · Noida, Uttar Pradesh, India

Synapse design automation inc.

Senior Verification Engineer

Oct 2014 – Nov 2016 · 2 yrs 1 mo · Bengaluru, Karnataka, India

Client : Renesas, Broadcom and Sandisk
Worked on IP/SoC verification of multiple blocks.

Infosys

4 roles

Senior Design Verification Engineer

Oct 2013 – Jan 2014 · 3 mos

Client : Intel Corp.
Wrote Master driver component according protocol and connect it at master agent.
Add features like calculation of Strobe,simultaneous read and write,bus width,burst size and burst length according to axi protocol.
Followed OVM methodology.
Instantiate in at testbench's top module through env and agent class.
Add different testcases in test library to test the functionality of driver and connect testlib through sequencer in agent clsss.

VerilogSystemVerilogUVMAXI ProtocolASIC VerificationSoC Verification

Full chip validation Engineer

Promoted

Jan 2013 – Oct 2013 · 9 mos

Client : Intel Corp.
Analyzing bugs according Intel Architecture and debugging.
Responsible for few testlists debugging.
Worked on assembly level testcase tracing and debugging.
Responsible for client specific tools.

DebuggingTestlist DebuggingFull-chip Validation

Automation Engineer

Aug 2012 – Nov 2012 · 3 mos · bangalore,india

Client : Intel Corp.
Written and modified perl scripts which is used for RTL designer's.
Reading Xl sheet mapping data into RTL.

Perl ScriptingRTL DesignAutomationScripting

Training on design and verification modules,Methodology,Protocols

May 2011 – Sep 2011 · 4 mos · Infosys, Bangalore

Practice on write code in Verilog for the design of some small entity's and verified them using system verilog.
Ramped up and practice on OVM/UVM methodology.
Practice on Perl/Shell assignments.
Ramped on protocols like AXI,AHB,I2c.

VerilogSystemVerilogOVM/UVM MethodologyDesign VerificationMethodology

Intel corporation

Visa Automation tool Development

Sep 2011 – Aug 2012 · 11 mos · bangalore

Design debug tool to trace the defects in RTL.
Wrote a perl scripts to generate the hierarchy of RTL first and then grep the faulty signal's from RTL files and inserts them into structure(this for hierarchy).
Update the RTL after insertion like port mapping for inserted signal's.
At the end it is easy to trace the faulty signals which was showing the wrong values in logic analyzer tool.

PerlDebug Tool DesignDebuggingTool Development