Vijeth Kulakarni

Software Engineer

Bengaluru, Karnataka, India14 yrs 7 mos experience
Highly Stable

Key Highlights

  • Expert in SRAM memory layout design.
  • Proven leadership in engineering teams.
  • Strong problem-solving skills in complex projects.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in layout design and project management.

Contact

LinkedIn

Skills

Core Skills

Engineering LeadershipProject ManagementCadence Virtuoso Layout Editor

Other Skills

Resource PlanningProblem SolvingDesign Rule Checking (DRC)Presentation SkillsEDALinuxLayout Versus Schematic (LVS)Transformational LeadershipDifficult SituationsProfessional DevelopmentEmployee EngagementTeam LeadershipDecision-MakingStress Management

Experience

14 yrs 7 mos
Total Experience
3 yrs 3 mos
Average Tenure
2 yrs
Current Experience

Samsung semiconductor

Senior Staff Engineer

May 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · On-site

  • Responsible for layout design and delivering SRAM memories with good quality.
  • Manage team members and resources for need basis and assigning various tasks.
  • Reviewer for technical paper presentations
Engineering Leadership

Qualcomm

3 roles

Lead Engineer

Nov 2020 – May 2024 · 3 yrs 6 mos

  • I was responsible for Layout Design of various CPU memories in different tech nodes and multiple foundries. Handle project from scratch till deliverable.
  • New resource on boarding procedures and training
  • Layout POC for different projects and interact with SOC team to align for dates and deliverables and quality
  • CWF reporting and management
  • Communicate with designers across different location and coordinate
  • Volunteer for Employee engagement activity
Cadence Virtuoso Layout EditorProject ManagementResource PlanningProblem SolvingDesign Rule Checking (DRC)Presentation Skills+3

Senior Engineer

Promoted

Jul 2017 – Oct 2020 · 3 yrs 3 mos

Cadence Virtuoso Layout EditorProject ManagementProblem SolvingDesign Rule Checking (DRC)Presentation SkillsEDA+2

Engineer 2

Aug 2014 – Jun 2017 · 2 yrs 10 mos

  • SRAM Compiler Layout Design
Cadence Virtuoso Layout EditorProblem SolvingDesign Rule Checking (DRC)Layout Versus Schematic (LVS)

Altran (sicontech)

Advanced Engineer

Aug 2014 – Jun 2017 · 2 yrs 10 mos · Bengaluru Area, India

  • Layout Engineer
Cadence Virtuoso Layout EditorProblem SolvingDesign Rule Checking (DRC)Presentation SkillsLayout Versus Schematic (LVS)

Amd

Layout Design Engineer

Jun 2013 – Jun 2014 · 1 yr · Bengaluru Area, India

  • Custom Memory Layout
Cadence Virtuoso Layout EditorProblem SolvingDesign Rule Checking (DRC)Layout Versus Schematic (LVS)

Sankalp semiconductors pvt ltd

Design Engineer

Aug 2012 – Jul 2014 · 1 yr 11 mos

  • Mixed Signal Physical Design
Cadence Virtuoso Layout EditorProblem SolvingDesign Rule Checking (DRC)Presentation SkillsLayout Versus Schematic (LVS)

Jsw steel ltd

DET

Aug 2008 – Sep 2009 · 1 yr 1 mo

Education

BVBCET, Hubli

Bachelor's Degree — Electrical & Electronics Engineering

Jan 2009 – Jan 2012

R.N.Shetty polytechnic, Sirsi

Diploma — Electrical & Electronics

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