Venkatesh Aluvala

Software Engineer

Hyderabad, Telangana, India2 yrs 8 mos experience

Key Highlights

Experienced in low-power design methodologies.
Proficient in static timing analysis and DRC.
Hands-on experience with Cadence tools.

Stackforce AI infers this person is a Silicon Design Engineer with expertise in low-power design and physical design methodologies.

Contact

Skills

Core Skills

Clock Tree SynthesisDesign Rule Checking (drc)Place & Route

Other Skills

Low-power DesignStatic Timing AnalysisUnixTCLLayout Versus Schematic (LVS)Cadence Virtuoso Layout Editor

Experience

2 yrs 8 mos

Total Experience

1 yr 11 mos

Average Tenure

9 mos

Current Experience

Amd

Silicon Design Engineer 2

Jul 2025 – Present · 9 mos · Hyderabad, Telangana, India · On-site

Clock Tree SynthesisDesign Rule Checking (DRC)

Soctronics

Physical Design Engineer

Aug 2023 – Jul 2025 · 1 yr 11 mos · Hyderabad, Telangana, India · On-site

Place & RouteClock Tree Synthesis

Amd veda iit

Internship Trainee

Apr 2023 – Jul 2023 · 3 mos · Hyderabad, Telangana, India · On-site

Education

JNTUH UNIVERSITY COLLEGE OF ENGINEERING JAGITYALA

Bachelor of Technology - BTech — Electronics & Communication Engineering

Aug 2020 – Jul 2023

JYOTHISHMATHI INSTITUTE OF TECHNOLOGY & SCIENCE THIMMAPUR

Diploma of Education — Electronics & Communication Engineering

Jun 2017 – Jun 2020

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