madhu shankara swamy pappu

Software Engineer

Bengaluru, Karnataka, India11 yrs experience
Highly Stable

Key Highlights

  • Expert in Physical Design and Timing.
  • Proven track record in semiconductor tech-file development.
  • Strong automation skills using Jenkins and SKILL.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing.

Contact

Skills

Core Skills

Physical DesignTiming

Other Skills

CMatlabMicrosoft OfficeC++VerilogMicrosoft ExcelMicrosoft WordProgrammingVHDLPerlJenkinsSKILL

Experience

11 yrs
Total Experience
4 yrs 11 mos
Average Tenure
1 yr 2 mos
Current Experience

Amd

Member of Technical Staff silicon design engineer

Mar 2025Present · 1 yr 2 mos · Bengaluru, Karnataka, India

TimingPhysical DesignCMatlabMicrosoft OfficeC+++6

Intel corporation

Design Engineer

Apr 2020Mar 2025 · 4 yrs 11 mos · Bengaluru, Karnataka

TimingPhysical Design

Infineon technologies

2 roles

Design Engineer

Feb 2016Mar 2020 · 4 yrs 1 mo · Bengaluru Area, India

  • Feb, 2016 - May, 2017
  • Tech-file development:
  • Helped in developing and testing the tech files for ICC/ICC2 environment for different technology nodes 40nm and 28nm
  • created the required test cases to verify the developed tech files and verifying the new updates for technologies ranging from 130nm to 65nm
  • Automated the tech-file verification using Jenkins.
  • June, 2017 - present
  • Physical Verification:
  • Performed Physical Verification for 40nm Automotive micro-controller designs.

Intern

Jul 2014May 2015 · 10 mos · Bengaluru Area, India · On-site

  • July, 2014 - June, 2015
  • Developed a method for checking the LVS (Layout Versus Schematic) correctness for the devices in the device library called "Device Library LVS check automation" using SKILL language.
  • This methodology can be used to make sure that the devices in the device libraries are made in accordance with the specification and also to cross check the consistency of LVS runsets at a very early stage

Education

NITK, surathkal

Master of Technology (M.Tech.) — VLSI DESIGN

Jan 2013Jan 2015

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