Vishweshwara B

Software Engineer

Bengaluru, Karnataka, India4 yrs 4 mos experience

Key Highlights

  • Expert in ASIC Design and CPU Architecture.
  • Proven track record in RTL coding and verification.
  • Strong experience in IP integration for leading semiconductor clients.
Stackforce AI infers this person is a semiconductor design engineer with expertise in ASIC and CPU architecture.

Contact

Skills

Core Skills

Rtl CodingScriptingAsic DesignCpu MicroarchitectureCpu ArchitectureIp IntegrationSoc Verification

Other Skills

RDCLogic SynthesisECOSystem VerilogLintCDCDFTSTADigital Circuit DesignVerilogScalaCircuit DesignMatlabC (Programming Language)Embedded Systems

About

An Electronics and Communication Engineer from VIT University with an interest in learning and working in the VLSI industry which began with an internship in IP Integration and SOC Verification that gave me great industry exposure and then gained armful experience from singularity dynamics whereby understanding the entire architecture of a micro-processor and verifying its formal verification. After this became an integration engineer at cerium(for intel client) exploring the flow & process of integrating an IP into SOC along with understanding its arch/req over the connections established and also working on IP level design in terms of packaging and checking over through lint, CDC, DFT, Synth, UPF and other backend flows. The previous experience helped in knowing the use of respective languages and tools to execute the real-world requirements of semiconductor industries, and looking forward to seeking more opportunities to enrich my knowledge and demonstrate my learning. Area of Intreset => $ ASIC Design $ CPU Architecture Skills => % Language: Verilog, System Verilog , C/C++. % Scripting: Perl, tcl

Experience

4 yrs 4 mos
Total Experience
2 yrs 5 mos
Average Tenure
1 yr 11 mos
Current Experience

Amd

Sr. Silicon Design Engineer

Jun 2024Present · 1 yr 11 mos · Bengaluru, Karnataka, India · Hybrid

  • > As part of IP team, worked on Integration & design correctness by necessary RTL updates validating through LINTing & also based on clock/Reset Arch understanding, worked on resolving CDC and RDC issues faced through RTL design changes, constraints and waivers.
  • > Working on Synthesis and ECO implementation.
  • > Worked on Scripting & various jobs execution w.r.t tool related enablement enhancing methodology and required Automation.
RTL CodingScripting

Cerium systems

RTL Design Engineer

Dec 2021May 2024 · 2 yrs 5 mos · Bengaluru, Karnataka, India

  • Worked on IP TFM team owning a IP and being responsible of enabling and ensuring violation free over LINT, CDC, SGDFT, VCLP, Synthesis, FEV, SAGE.
  • Also Worked on IP integration by owning a IP and being responsible over its integration as per the architecture and being sure its out of any downline bugs over the flow for Intel Client
ASIC DesignRTL Coding

Singularity dynamics pvt ltd

2 roles

Verification Engineer

Aug 2021Sep 2021 · 1 mo · India

  • Continued the process with SWERV CPU by analyzing deeper with each stage beginning with FETCH till COMMIT stage.
CPU Microarchitecture

Chip Verification Engineer

Mar 2021Jul 2021 · 4 mos · India

  • Worked completely on computer architecture and extracting its micro-architecture by analyzing 5 stage pipelined ZIP CPU based on RISCV ISA and started the same process with 9 stage pipelined dual issue superscalar SWERV CPU based on RISCV ISA.
CPU Architecture

Sifive

Intern

Jan 2020Sep 2020 · 8 mos · Bengaluru Area, India

  • IP On-boarding and SOC Verification
IP IntegrationSOC Verification

Hewlett packard enterprise

Summer Internship

May 2019Jun 2019 · 1 mo · Chennai Area, India

  • Design and implementation of 8 bit RISC Processor using Verilog HDL

Education

Remote Customer Service Jobs

BTech - Bachelor of Technology — electrons

Jan 2016Jan 2020

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